A 700MHz-BW –164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving <-85dBFS HD3 using Digital Cancellation of DAC Errors The 2nd stage’s (Fig. 22.2.2) relaxed NSD allows a low-area RC lattice delay and a PMOSonly current-steering sub-DAC without negative supplies. The flash sub-ADC is identical to the one in the 1st stage, while the interstage filter is an impedance-scaled version of its 1st-stage counterpart. The 3rd stage is a VCO ADC with a V-to-I converter and a phaseinterpolated ring oscillator with over-range and nonlinearity corrections [3].

📋 论文概要

该论文提出了一种连续时间流水线ADC，通过片上数字重建滤波器结合PRBS注入和两步FIR-to-IIR转换来估计模拟传递函数，从而消除子ADC量化误差，实现了700MHz带宽和-164dBFS/Hz的小信号噪声频谱密度，功耗703mW。

💡 主要创新点

• 采用片上数字重建滤波器，通过PRBS注入和交叉相关估计模拟传递函数，实现高带宽和低噪声性能。
• 将传递函数估计扩展为两步，分别处理两个DRF部分，提高估计精度（误差分别<0.1%和<1%）。
• 通过连续时间流水线架构结合数字校准，在700MHz带宽内达到极低的噪声频谱密度。

🏷 关键词

📄 原文摘要

Qingnan Yu3, Zhao Li1, Zeynep Lulec1, Konstantinos Vasilakopoulos1, Prawal Shrestha2, Donald Paterson4, Raviteja Theertham1, Aseer Chowdhury5 The DRF (Fig. 22.2.1) combines stage outputs such that sub-ADC quantization errors, eq1 and eq2, are cancelled. This requires the analog transfer functions (TFs) traversed by eq1 and eq2 to be estimated – with respectively <0.1% and <1% error – and implemented in the DRF. TFs are estimated by PRBS injection via PRBS DACs, followed by crosscorrelation and FIR-to-IIR conversion [3], but now extended to two steps for two DRF sections: using PRBS2/D3 cross-correlation to obtain A2/B2 filter coefficients and PRBS1/DO2 cross-correlation for those of A1/B1 filters. Equalization filter EQ compensates band-edge droop. For high accuracy, the PRBS DACs are implemented as copies of the sub-DAC UEs, with careful layout to minimize mismatch. The larger area of resistors

👥 作者与机构

Sharvil Patil1, Asha Ganesan1, Hajime Shibata1, Victor Kozlov1, Gerry Taylor2,