⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种基于顶层金属和C4平面螺旋电感的单片集成降压稳压器，在16nm工艺上实现了10.5W/mm²的功率密度和600MHz的开关频率，解决了为不同IP提供多个独立电压轨的问题。
Sheldon Weng, Anne Augustine, Huong T. Do, Jingshu Yu, Phong D. Bach, Xiaosen Liu, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De Intel, Hillsboro, OR With the industry moving to a disaggregated approach to constructing modern complex SoC designs, a large variety of digital, IO and PHY IP blocks are needed to be integrated on multiple advanced CMOS processes. Each IP on any given process node desires an optimal voltage to meet its performance and power efficiency goals. Delivering the aggregated sum of unique rails across all IPs, across die-stacks from the platform is extremely challenging, given the shrinking form factors of modern electronic systems. Furthermore, to maximize battery life, these IP blocks are actively lowering voltages, and are utilizing workload or activity-based supply voltages, like traditional DVFS, necessitating the need for localized voltage regulators (VR).
Suhwan Kim, Harish K Krishnamurthy, Zakir Ahmed, Nachiket Desai,