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ISSCC 2024Session 9 · NOISE-SHAPING AND SAR ADCsData Converters

A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs

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📋 论文概要

本文提出了一种时间交织的管道SAR ADC,通过共享残差积分放大器实现了高能效,解决了传统CTDSM在宽带下设计复杂和传统pipeline功耗高的问题。该ADC在200MHz带宽下达到71dB SNDR,FoMs为173dB。

💡 主要创新点

核心指标
71dB SNDR @ 200MHz BW, FoMs 173dB
重要性
发表年份
ISSCC 2024

🏷 关键词

管道SAR ADC时间交织共享残差积分放大器高FoMs宽带ADC

📄 原文摘要

Wideband (BW >100MHz) and high-dynamic-range (DR >70dB) ADCs are in high demand for next-generation wireless standards. Conventional ADC solutions face challenges in both performance and efficiency: CTDSMs demonstrate favorable DR within moderate bandwidths, but their design complexity escalates significantly when addressing wider BW due to their closed-loop nature. Conventional pipeline ADCs can achieve high BW and resolution, but this comes at the expense of high power consumption caused by the inter-stage amplifiers. The hybrid architecture of the pipeSAR presents an appealing combination of high resolution and improved efficiency by taking advantage of the SAR architecture, which makes them well-suited for mobile devices. Nonetheless, the conversion rate of the pipe-SAR ADC remains restricted. To solve this challenge, this work presents an interleaved pipe-SAR architecture with a shared residue integrating amplifier. It improves the opamp efficiency by eliminating the

👥 作者与机构

Xiyu He, Mingyang Gu, Hanjun Jiang, Yi Zhong, Nan Sun, Lu Jie

Tsinghua University, Beijing, China

分类:Data Converters · 年份:ISSCC 2024