A 3nm Adaptive Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion

📋 论文概要

本文提出了一种在3nm工艺下的自适应时钟占空比控制器，用于缓解晶体管老化引起的时钟占空比失真问题。该控制器通过动态调整时钟占空比，补偿因时钟门控导致的老化效应，从而保证高性能处理器（如CPU、GPU、NPU）的时钟稳定性。

💡 主要创新点

• 提出自适应时钟占空比控制技术，动态补偿老化引起的时钟路径延迟不对称。
• 在3nm先进工艺节点上实现，针对时钟门控导致的老化效应进行优化。

🏷 关键词

📄 原文摘要

Felipe Cabral3, Jason Hu2, Rajan Verma2, Vamshidhar Chiranji2, Anil Kumar2, Santanu Sarma2, Keith Bowman1 Qualcomm, Raleigh, NC Qualcomm, San Diego, CA 3 Qualcomm, Cork, Ireland 1 2 The clock path of a high-performance processor (e.g., CPU, GPU, NPU) contains many clock inverters, MUX gates, and clock-gating circuits (CGCs) from the phase-locked loop (PLL) to the numerous clock-leaf nodes driving the sequential circuits. When clock gating prevents clock toggling for extended periods of time to reduce power, the rising and falling clock-path delays change differently due to transistor aging, where only alternate transistors in the path degrade (Fig. 14.3.1) [1]. The falling input transition propagates through stressed transistors, and thus, slows down. In contrast, the rising input transition speeds up by propagating though unstressed transistors with less contention from the stressed devices. As a result, a clock duty-cycle distortion (DCD) accumulates

👥 作者与机构

Daniel Yingling1, Yimai Peng1, Robert Vachon1, Dipti Pal2, Sagar Jariwala2,