A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets

📋 论文概要

该论文提出了一种采用4nm工艺的48Gb/s/线单端NRZ并行收发器，针对下一代高带宽内存和芯片互连需求，通过偏移校准和均衡方案解决了高速单端信号传输中的信号完整性问题。

💡 主要创新点

• 提出了一种单端NRZ并行收发器架构，在4nm节点实现48Gb/s每线的数据速率，适用于高密度互连。
• 集成了偏移校准和均衡方案，用于补偿工艺变化和信道损耗，提升信号质量。

🏷 关键词

📄 原文摘要

Hyemun Lee, Juyoung Kim, Eunsu Kim, Yeongeon Kang, Gunhu Mo, Youjin Lee, Mingyeong Kim, Seongno Lee, Donguk Park, Byoung-Joo Yoo, Hyo-Gyuem Rhew, Jongshin Shin Samsung Electronics, Hwaseong, Korea With the development of industries, such as high-performance computing, advanced driver-assistance systems, artificial intelligence, and deep learning, demand for highbandwidth memory, and chiplets continues to increase. Most of these applications generally use a source-synchronous single-ended parallel transceiver architecture and consist of a 2.5D package (called an advanced package) along with silicon interposer channels [1]. Applications also include a lot of high-speed I/O to process large amounts of data. In general, to achieve high-speed operation and high performance, bandwidth extension techniques, such as inductors and a continuous-time linear equalizer, and calibration schemes, such as slicer-offset calibration and skew calibration, between data

👥 作者与机构

Kihwan Seong, Wooseuk Oh, Hyunwoo Lee, Gyeomje Bae, Youngseob Suh,