A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

📋 论文概要

该论文提出了一种7GHz数字锁相环，采用级联分数分频器和伪差分数字时间转换器（DTC），有效抑制了分数杂散，实现了-62.1dBc的分数杂散性能。解决了传统DTC在分数N锁相环中量化噪声消除的局限性。

💡 主要创新点

• 提出级联分数分频器结构，降低多模分频器量化噪声对杂散的影响。
• 采用伪差分DTC架构，提高线性度并进一步抑制分数杂散。

🏷 关键词

📄 原文摘要

Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada Tokyo Institute of Technology, Tokyo, Japan Modern wireless transceivers and FMCW radar systems are demanding stringent specifications on PLL integrated jitter and spur performance for lower EVM and higher position accuracy. To achieve lower jitter, a digital-to-time converter (DTC) is usually used in fractional-N PLLs to cancel the quantization noise (QN) from delta-sigma modulation (DSM), which is used to control the multi-modulus divider (MMD) [1]. However, the integral non-linearity (INL) of DTCs causes periodic patterns at the input of the phase detector (PD), leading to fractional spurs. Some conventional PLLs use dither to mitigate the fractional spur problem [2-4]. Although the dither-based techniques show a strong suppression in fractional spurs, the power of those spurs still remains in

👥 作者与机构

Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang,