A 14GHz Chopper-Refolding Sampling PLL Achieving 33.8fsrms and 80.8dBc Reference Spur with a kT/C-Noise-Cancellation SPD

📋 论文概要

本文提出了一种14GHz斩波-折叠采样锁相环（PLL），集成了kT/C噪声消除采样鉴相器（SPD）和自注入压控振荡器（VCO）。该设计通过解耦抖动与鉴相增益、滤除闪烁噪声，实现了33.8fsrms的低抖动和-80.8dBc的高参考杂散抑制。

💡 主要创新点

• 提出kT/C噪声消除采样鉴相器（SPD），将抖动与相位检测增益解耦，降低了热噪声影响。
• 采用斩波-折叠（chopper-refolding）方案抑制闪烁噪声，提升了低频相位噪声性能。
• 引入自注入VCO结合谐波阻抗扩展技术，无需手动调谐即可实现高优值（FoM）。

🏷 关键词

📄 原文摘要

Abstract A 14GHz chopper-refolding sampling PLL is implemented in 28nm CMOS, integrating a kT/C-noise-cancellation sampling phase detector (SPD) and a self-injection VCO with harmonic-impedance expansion. The SPD decouples jitter and phase-detection gain, while the chopper-refolding scheme filters flicker noise. The VCO enables a high FoM without manual tuning, achieving 33.8fsrms jitter, -80.8dBc spur, 16.9mW power, and competitive jitter performance among integer-N PLLs. In high-speed RF direct-sampling systems, a low-jitter phase-locked loop (PLL) is critical for providing precise clock signals to ADCs, thereby enabling accurate signal capture and processing. Such systems impose stringent requirements on PLL performance, particularly in terms of low jitter and low phase noise—both of which are essential for maintaining high dynamic range and signal fidelity [1]. First, the PLL rms jitter must be tightly controlled to

👥 作者与机构

Yichen Liu, Jian Zhang, Xiaosen Liu, Yan Wang

Tsinghua University, Beijing, China