A 14GHz Ring-Based 3rd-Order Fractional-N PLL with 164fsrms Jitter and a 100MHz Reference

📋 论文概要

该论文提出一种基于环形振荡器的14GHz三阶分数-N锁相环，采用级联子采样延迟锁定环（DLL）和窄脉冲积分器来抑制相位噪声与电源噪声，实现了164fs_rms的超低抖动。通过三态极性可逆SSPD减少DTC范围与带宽退化，并应用延迟校准优化VCDL延迟范围与占空比，解决了高频低抖动PLL的设计挑战。

💡 主要创新点

• 级联子采样DLL在type-II PLL输出端额外抑制相位噪声与电源噪声，提升噪声性能。
• 采用窄脉冲积分器降低子采样DLL中的积分抖动，改善整体抖动。
• 使用三态极性可逆SSPD减少DTC范围与带宽退化，同时通过延迟校准缩小VCDL延迟范围并校准占空比。

🏷 关键词

📄 原文摘要

Abstract This work presents a 14GHz ring-based 3rd-order fractional-N PLL with 164fsrms jitter and a 100MHz reference. A sub-sampling DLL is cascaded in the type-II PLL output for extra phase-noise and supply-noise suppression. A narrow-pulsed integrator is used in the sub- sampling DLL to reduce integrated jitter. A tri-state polarity-reversible SSPD is employed to reduce the DTC range and bandwidth degradation. Delay calibration is applied to reduce the VCDL delay range and implement the VCDL duty-cycle calibration. A low-jitter phase-locked loop (PLL) is a critical building block in high-speed wireline transceivers, such as serializer/deserializer (SerDes) systems. Fractional-N operation with fine frequency resolution is required to accommodate different crystal frequencies. Ringoscillator (RO)-based PLLs are particularly attractive for such applications due to their compact area and ease of integration. However, RO-based PLLs suffer from poor phase

👥 作者与机构

Zhaochen Zhu, Qingxuan Lin, Zhiqiang Huang

Hong Kong University of Science and Technology, Guangzhou, China