A 76.7fs-Integrated-Jitter and -71.9dBc In-Band FractionalSpur Bang-Bang Digital PLL Based on an Inverse-ConstantSlope DTC and FCW Subtractive Dithering

📋 论文概要

提出了一种基于逆常数斜率数字时间转换器（DTC）的Bang-Bang数字锁相环（BBPLL），实现了76.7fs的积分抖动和-71.9dBc的带内分数杂散，解决了分数-N模式下量化误差导致性能降级的问题。

💡 主要创新点

• 采用逆常数斜率DTC技术，有效抑制了分数杂散，提升了频谱纯度。
• 通过优化环路设计，在Bang-Bang PLL中实现了超低抖动和高分辨率频率合成。

🏷 关键词

📄 原文摘要

Luca Bertulessi1, Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milano, Italy, 2Infineon Technologies, Villach, Austria 1 Ultra-low-jitter and high-spectral-purity frequency synthesizers are key building blocks for high-performance wireless transceivers and FMCW radars. A bang-bang PLL (BBPLL) is an attractive solution thanks to its small footprint and low power consumption; however, its operation in the fractional-N mode is hindered by the large quantization error (Q-error) caused by the non-integer frequency multiplication saturating the narrow input range of the bang-bang phase detector (BBPD). A digital-to-time converter (DTC) is typically used to cancel the Q-error in time domain [1] (Fig. 4.3.1 top-left). Unfortunately, the DTC non-linearity can generate significant fractional spurs, thus corrupting the PLL spectral purity and integrated jitter. Solutions to this problem rely on

👥 作者与机构

Simone M. Dartizio1, Francesco Tesolin1, Giacomo Castoro1,

Francesco Buccoleri1, Luca Lanzoni1, Michele Rossoni1, Dmytro Cherniak2,