A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoMJ Including the XO Power and Noise voltages as low as 0.28V for low-power VCO implementation, with the possibility to go up to 0.45V without risking gate-dielectric breakdown if lower out-of-band noise is needed. The performance of the VCO is further enhanced by the second-harmonic-resonance method applied at both supply and ground sides [18,19].

📋 论文概要

本文提出了一种4.6GHz锁相环与晶振协同设计，采用自对准脉冲注入驱动器，实现了63.3fs rms的抖动和-255.2dB的品质因数（FoMJ）。该设计通过分析注入角度与相位噪声的关系，优化了XO的噪声性能，解决了传统设计中PLL与XO相互干扰的问题。

💡 主要创新点

• 提出自对准脉冲注入驱动器，实现PLL与XO的协同设计，降低整体抖动。
• 推导出XO相位噪声与注入角度的关系式，并通过仿真验证，为低噪声设计提供理论指导。
• 在4.6GHz频率下实现63.3fs rms超低抖动，FoMJ达到-255.2dB，包含XO的贡献。

🏷 关键词

📄 原文摘要

Figure 19.10.3 shows the details of the proposed pulse-injection XO driver and its noise characteristics. Figure 19.10.3 (left) shows the theoretical calculation and the simulation of the XO phase-noise (PN) floor (PNXO) in accordance with the injection angle (θ) from the peak point, and the phase noise of the clock generating the injection pulse (PNINJ). Assuming injection jitter (∆tINJ) and the resultant XO voltage error (∆V) to be infinitesimal, PNXO is derived as PNINJ + 20log10(sin|θ|), which is plotted together with the simulation results for three different injection-pulse phase-noise levels. Since the injection-noise-to-phase-noise conversion increases with θ and PNINJ, the pulse-injection timing must be controlled accurately with the lowest jitter possible. Both requirements are satisfied by selecting pulses from the VCO output located at N/4 and 3N/4 VCO cycles after the crossing point of the XO

👥 作者与机构

Can Livanelioglu*, Long He*, Jiang Gong*, Sina Arjmandpour, Gabriele Atzeni, Taekwang Jang