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ISSCC 2025Session 19 · FREQUENCY SYNTHESIZERS AND SERIES-RESONANCE VCOSClocking & PLLs28nm CMOS

A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and -56dBc Worst-Case Spur Using ILO Filter in 28nm CMOS

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📋 论文概要

本文提出了一种60GHz的I/Q校准单边带混频器本振(LO),采用注入锁定振荡器(ILO)滤波器,实现了亚纳秒建立时间和-56dBc最差杂散,适用于联合通信与雷达感知(JCAS)系统。

💡 主要创新点

工艺节点
28nm CMOS
重要性
发表年份
ISSCC 2025

🏷 关键词

60GHzI/Q校准SSB混频器本振亚纳秒建立时间杂散ILO滤波器JCAS

📄 原文摘要

University of California, Santa Babara, CA 3 Korea Aerospace Research Institute, Daejeon, Korea 1 2 Joint communication and radar sensing (JCAS) has been gaining much attention for its efficient use of spectrum, particularly in applications such as autonomous vehicles and 6G systems. Among the various modulation schemes for JCAS, OFDM is favored as it offers robustness against interference in radar sensing and enables high data-rate communication. Additionally, implementing JCAS in the mm-wave band is highly preferred, as it provides the large bandwidth necessary to increase radar resolution and data-rate. However, the wide bandwidth in mm-wave poses a significant challenge for the receiver-end ADC. A promising approach to address this challenge is the stepped-carrier (SC)-OFDM scheme [1,2], which divides the wide RF bandwidth into smaller, frequency-hopped bands, thereby reducing the ADC bandwidth requirements. Unfortunately, the SC-OFDM imposes stringent requirements

👥 作者与机构

Jaewon Oh1, Cheol So2, Hyojun Kim3, Songcheol Hong1, SeongHwan Cho1

KAIST, Daejeon, Korea

分类:Clocking & PLLs · 年份:ISSCC 2025