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ISSCC 2025Session 19 · FREQUENCY SYNTHESIZERS AND SERIES-RESONANCE VCOSClocking & PLLs

A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms

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📋 论文概要

本文提出了一种27GHz分数N子采样PLL,采用极性可逆的SSPD结构,实现了57.9fs rms抖动、-249.7dB FoM和1.98µs锁定时间,解决了毫米波分数N PLL在高速通信中需要低抖动和快速锁定的问题。

💡 主要创新点

核心指标
57.9fs rms jitter, -249.7dB FoM, 1.98µs locking time
重要性
发表年份
ISSCC 2025

🏷 关键词

分数N PLL子采样PLL低抖动快速锁定毫米波

📄 原文摘要

Haoran Li1, Jinge Li1, Xueying Jiang1, Xi Meng1, Jun Yin1, Rui P. Martins1,2, Pui-In Mak1 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Millimeter-wave (mm-wave) fractional-N (FN) PLLs with an rms jitter of <100fs are demanded by high-speed communication systems to realize precise channel selection [1] or accommodate different crystal frequencies [2]. Equipped with high-gain phase detectors (PDs), the FN sampling PLLs (SPLLs) [3,4] and bang-bang PLLs (BBPLLs) [5-7] utilizing DTCs to cancel the quantization error (Q-error) from the multi-modulus divider (MMD) controlled by a delta-sigma modulator (DSM) have demonstrated superior jitter when synthesizing sub-15GHz outputs. In these FN-PLLs, the DTC is the most challenging block since it contributes substantial in-band phase noise (PN), and its nonlinearity increases the fractional (frac.) spur and noise folding. By directly driving the MMD with oscillator outputs,

👥 作者与机构

Jitter, -249.7dB FoM, and 1.98µs Locking Time Using a, Polarity-Reversible SSPD

分类:Clocking & PLLs · 年份:ISSCC 2025