A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration constructed DAC voltage (VDAC) is shaped with a high slope (SDAC) in the gain-boosted PD, a high SDAC is achieved by generating a slope on VDAC in the gain-boosted PD, and the DTC delay is used to compensate for the timing error from CLKFB to the voltage crossing.

📋 论文概要

本文提出一种采用32kHz低频参考的2.4GHz分数N非均匀过采样PLL，通过增益增强的鉴相器和环路增益校准技术，解决了传统过采样PLL中因低频参考导致的电压噪声引起的抖动恶化问题。

💡 主要创新点

• 提出增益增强的鉴相器，通过提高转换速率降低电压噪声引起的抖动。
• 采用非均匀过采样技术和环路增益校准，实现低频参考下的高频输出与低抖动性能。

🏷 关键词

📄 原文摘要

Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada Figure 4.4.3 illustrates the proposed gain-boosted PD. In the conventional OSPLL, the slew rate of the DAC signal, SDAC, keeps 0. The voltage-noise-induced jitter in the PD, &tVN,PD increases as SREF decreases. For example, at the 0-degree phase, SREF is near 100V/ms while 30V/ms at the 80-degree phase. The induced &tVN,PD rms values are near 500ps and 1500ps, respectively, and can only be reduced by a higher fREF, e.g., 10 times suppression with a 320kHz REF. To solve this issue, the sloped VDAC is generated to reduce &tVN,PD and increase PD gain (KPD). SDAC is always of opposite polarity to SREF. According to a transistor-level simulation, the SDAC is near -120000V/ms at the 0-degree phase. This corresponds to a near 2ps rms &tVN,PD. This can be seen from a &tVN,PD comparison plot. With the gain-boosted PD, SDAC can help suppress &tVN,PD effectively

👥 作者与机构

Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang,