A 0.65-to-1V-VDD 10.5-to-11.85GHz Fractional-N Sampling PLL Achieving 71.47fs Integrated Jitter and <-60dBc Near-Integer Fractional Spur in 40nm CMOS

📋 论文概要

本文提出了一款工作在0.65-1V宽电压范围内的10.5-11.85GHz分数N采样PLL，解决了低电压下相位噪声差、常规电压下可靠性、非线性和小分数频率控制字收敛问题。采用量化误差减少的宽电压采样鉴相器、高线性度两级数字时间转换器和抖动方法，在40nm工艺下实现了71.47fs积分抖动和-251.8dB FoM。

💡 主要创新点

• 提出宽电压范围量化误差减少的采样鉴相器（QE-reduction WV SPD），改善低电压下相位噪声并保证常规电压可靠性。
• 设计高线性度两级数字时间转换器（2-stage DTC），降低非线性影响。
• 采用数字校准辅助的量化误差抖动方法（DCC-aided QE dithering），解决小分数频率控制字下的收敛问题并降低近整数杂散。

🏷 关键词

📄 原文摘要

Abstract This paper presents a 0.65-to-1V, 10.5-to-11.85GHz wide-VDD-range (WV) fractional-N sampling PLL. The QE-reduction WV SPD, high-linearity 2-stage DTC, and DCC-aided QE dithering method are proposed to address the issue of poor phase noise at low-VDD, reliability at regular VDD, nonlinearity, and convergence issues at small fractional FCWs. The 40nm prototype achieves 71.47fs jitter, –251.8dB FoM, and <–60dBc near-integer spur. Dynamically varying supply voltage (VDD) is attractive for digital-centric system on chips (SoC) to meet throughput and power-consumption requirements in different scenarios [1]. To meet the performance requirements of wireless transceivers in the SoCs, the phaselocked loop (PLL) with high spectral purity and high spectrum-utilization efficiency is crucial. Therefore, a fractional-N PLL (FN-PLL) that achieves low jitter and low spur across a wide dynamic voltage operating range (WV) is highly desirable. Several high-performance FNPLLs operating at regu

👥 作者与机构

Yixi Li1,2, Junjie Chen1,2, Xinyu Shen1, Jie Yang3, Jian Liu1,2, Nanjian Wu1,2, Zhao Zhang1,2, Liyuan Liu1,2

Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China, 2University of Chinese Academy of Sciences, Beijing, China, 3Westlake University, Hangzhou, China