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ISSCC 2026Session 27 · FREQUENCY GENERATORS, MULTIPLIERS AND MODULATORSClocking & PLLs28nm CMOS

A 77GHz 8-bit CMOS Phase Shifter Adopting a Nested-Vector-Based Error Correction with 0.33°/0.07dB RMS-Error for MIMO Radar Applications

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📋 论文概要

本文提出了一种77GHz 8位嵌套向量和相移器,采用28nm CMOS工艺。通过将单个外向量分裂为两个内向量,并结合峰值误差平滑技术,有效抑制了I/Q失配,实现了0.33°的均方根相位误差和0.065dB的均方根增益误差,核心面积仅0.17mm²,适用于MIMO雷达系统。

💡 主要创新点

核心指标
0.33° rms相位误差, 0.065dB rms增益误差
工艺节点
28nm CMOS
重要性
发表年份
ISSCC 2026

🏷 关键词

77GHz相移器嵌套向量和误差校正MIMO雷达

📄 原文摘要

Abstract In this paper, we present a 77GHz 8-bit nested vector-sum phase shifter in 28nm CMOS. The architecture performs vector modulation by splitting a single outer vector into two inner vectors generated by a two-stage I/Q coupler. Owing to its insensitivity to I/Q mismatch and the peak error smoothing technique, the phase shifter achieves 0.33° and 0.065dB rms phase and gain errors while occupying a core area of 0.17mm2. With the recent advancements in advanced driver-assistance systems (ADAS), millimeterwave (mm-wave) phased-array RFICs have attracted attention as key technologies for radar systems in autonomous driving [1] and are expected to expand into various fields such as robotics and mobile applications. In multiple-input-multiple-output (MIMO) radar systems, phased-array architecture is required to increase the detection range and achieve high angular resolution. A vector-sum phase shifter (VSPS) achieves 360° phase-shifting range

👥 作者与机构

Geonho Park, Byeong-Taek Moon, Kyunghwan Kim, Doyoon Kim, Goeun Baek, Byungho Yook, Hyun-Chul Park, Chan-Hong Park

Samsung Electronics, Hwaseong, Korea

分类:Clocking & PLLs · 年份:ISSCC 2026