A –66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC

📋 论文概要

该论文提出了一种采用逆恒斜率DTC的分数-N数字PLL，用于抑制电源扰动，无需额外校准或额外电源不敏感模块。在分数-N模式下，当DTC电源施加10mVpp正弦扰动时，PLL实现了低于59fs的积分抖动、低于-66dBc的分数杂散，以及-251.4dB的抖动-功耗品质因数。

💡 主要创新点

• 提出逆恒斜率DTC技术，有效抑制电源扰动对PLL性能的影响。
• 无需额外校准或额外电源不敏感模块，简化了系统设计。

🏷 关键词

📄 原文摘要

inverse-constant-slope DTC for rejection of supply disturbances is presented. Compared to traditional fractional-N digital PLLs, it requires no additional calibration for supply rejection or additional supply-insensitive blocks. The PLL achieves integrated jitter below 59fs under 10mVpp sinusoidal disturbance applied to the DTC supply in the fractional-N mode, with fractional spurs below -66dBc and the jitter-vs-power figure of merit of -251.4dB. Modern systems-on-chip for wireless/wireline communications typically integrate multiple functional blocks, including several frequency synthesizers, within a compact silicon area. In this context, sensitivity to supply disturbances—arising either from crosstalk between adjacent sub-blocks or by DC/DC converters and low-dropout regulators in the power supply

👥 作者与机构

Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Politecnico di Milano, Milan, Italy Abstract A fractional-N digital PLL adopting a pseudo-differential