A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a TimeMode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

📋 论文概要

该论文提出了一种基于时间模式算术单元的分数-N数字锁相环，通过精确抵消预测的瞬时时间偏移来最小化相位检测器输入范围，从而改善线性度和抑制噪声。芯片在2.6-4.1GHz频率范围内实现了-249.4dB FoM和-59dBc分数杂散性能。

💡 主要创新点

• 提出时间模式算术单元，能够预测并抵消瞬时时间偏移，显著减小相位检测器输入范围。
• 通过最小化相位检测器输入范围，提高了线性度和相位检测器增益，抑制了后续环路组件的噪声贡献。
• 实现了高FoM和低分数杂散，性能优于传统设计。

🏷 关键词

📄 原文摘要

Peng Chen3, Gerd Spalink2, Ben Eitel2, Ken Yamamoto4, Robert Bogdan Staszewski1,3, Morteza S. Alavi1, Masoud Babaie1 Delft University of Technology, Delft, The Netherlands Sony Europe, Stuttgart, Germany 3 University College Dublin, Dublin, Ireland 4 Sony Semiconductor Solutions, Atsugi, Japan 1 2 In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable oscillator-clock (CKV) edges prior to the PD. There are currently two main cancellation strategies. The first is to align FREF and CKV by inserting a digital-to-time converter (DTC) on either path. However, due to the DTC nonlinearity and its susceptibility to PVT variations, the PLL can suffer from large fractional spurs. Although

👥 作者与机构

Zhong Gao1, Jingchu He1, Martin Fritz2, Jiang Gong1, Yiyu Shen1, Zhirui Zong1,