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ISSCC 2025Session 19 · FREQUENCY SYNTHESIZERS AND SERIES-RESONANCE VCOSClocking & PLLs

An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz

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📋 论文概要

本文提出了一种8.1-9.9GHz单核伪串联谐振振荡器,通过新型谐振结构突破了传统并联谐振LC振荡器的品质因数限制,实现了-128.7dBc/Hz @1MHz的超低相位噪声,满足5G-Advanced和6G通信对高数据速率的需求。

💡 主要创新点

核心指标
-128.7dBc/Hz @1MHz offset, 8.1-9.9GHz tuning range
重要性
发表年份
ISSCC 2025

🏷 关键词

伪串联谐振振荡器低相位噪声5G/6G通信

📄 原文摘要

King’s College London, London, United Kingdom 1 2 As data-rate requirements in 5G-Advanced and future 6G communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring higher-order modulation schemes and ever-higher throughput. Under the CMOS-limited supply voltage and power-dissipation constraints, the PN in conventional parallel-resonance (PR) LC-tank oscillators is primarily limited by the tank quality factor (Q). To continue the quest for everlower PN, N oscillators can be coupled together for an effective PN reduction of 10log(N) (Fig. 19.4.1, top-right) [1]. However, the practical implementation of multicore oscillators is hampered by 1) mismatches between the cores, which degrades the achievable PN and figure of merit (FoM), and 2) the area-intensive floorplan required when coupling many cores. Series-resonance (SR) LC oscillators have the potential to achieve ultra-low PN with

👥 作者与机构

Jiawen Chen1, Kai Xu2, Teerachot Siriburanon1, Robert Bogdan Staszewski1

University College Dublin, Dublin, Ireland

分类:Clocking & PLLs · 年份:ISSCC 2025