A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

📋 论文概要

本文提出一种9.25GHz数字锁相环，采用多DTC拓扑实现分数杂散消除，通过重新对齐参考和分频器边沿来改善集成抖动，满足高速移动通信对低抖动本地振荡器的要求。

💡 主要创新点

• 提出基于多DTC拓扑的分数杂散消除技术，有效降低杂散干扰
• 通过DTC重对齐参考与分频器边沿，显著改善集成抖动性能

🏷 关键词

📄 原文摘要

Carlo Samori1, Andrea L. Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy, 2Infineon Technologies, Villach, Austria *Equally Credited Authors (ECAs) 1 The quest of increasingly higher mobile uplink/downlink data-rates has recently driven the communication industry to set extremely challenging requirements on the integrated jitter of local oscillators [1]. In fractional-N PLLs, the adoption of a digital-to-timeconverter (DTC) has become ubiquitous to meet performance targets, as it greatly improves integrated jitter by re-aligning the edges of the reference and the divider signals (top-left of Fig. 4.5.1) [1,2]. Unfortunately, any DTC non-linearity converts the quantization error (QE), driving the DTC into fractional spurs in the PLL spectrum, thus degrading the integrated jitter. Several digital techniques have been proposed to reduce the DTC non-linearity either at the cost of increasing hardware resources [3] or requiring

👥 作者与机构

Giacomo Castoro*1, Simone M. Dartizio*1, Francesco Tesolin1,

Francesco Buccoleri1, Michele Rossoni1, Dmytro Cherniak2, Luca Bertulessi1,