A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving –62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise

📋 论文概要

该论文提出了一种具有电源不敏感性的分数-N数字锁相环，通过背景校准环路实现可变斜率数字-时间转换器（DTC）的电源抑制，在不影响线性度和噪声的情况下，在10mVpp正弦电源纹波下实现了-62dBc的杂散和69fs的抖动。解决了高频收发器对低杂散、低抖动频率合成器的需求。

💡 主要创新点

• 提出了一种可变斜率DTC，通过背景校准环路实现电源不敏感性，无需额外线性度或噪声折衷。
• 在10kHz至50MHz的电源扰动频率范围内，实现了低于-62dBc的杂散和65.6fs的抖动，显著提升了电源噪声抑制能力。

🏷 关键词

📄 原文摘要

variable-slope digital-to-time converter (DTC) is presented. Supply insensitivity is achieved by a background calibration loop, without affecting DTC linearity or noise. Measured results demonstrate 65.6fs jitter upon 6.2mVrms supply noise and <−62dBc spurs under 10mVpp supply-ripple over 10k-to50MHz disturbance frequency range. The PLL covers 8.75-to-10.25GHz tuning range, while achieving a −251dB jitter-power figure of merit at 22.5mW power. Frequency synthesizers with spurious tones below -60dBc and jitter lower than 100fs are essential for high data rate wireless and wireline transceivers [1,2]. Digital-to-time converter (DTC)-based fractional-N PLLs have emerged as a compelling solution, effectively eliminating the quantization error associated with fractional frequency multiplication [3-7].

👥 作者与机构

Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni Rocco Trotta, Andrea Leonardo Lacaita,

Simone Mattia Dartizio, Salvatore Levantino Politecnico di Milano, Milan, Italy Abstract A 28nm fractional-N digital PLL with a supply-insensitive