A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth

📄 原文摘要

The W and D bands located at the lower boundary of the sub-THz spectrum are considered viable candidates for CMOS-based wireless-communication systems to utilize sub-THz frequencies. However, there are still many challenges to overcome before these bands can be put to practical use. One of the most critical challenges is the design of a frequency synthesizer to generate sub-THz local-oscillator (LO) signals with extremely low jitter. This is because the value of the rms jitter required to support the target EVM decreases as the LO frequency increases, e.g., the rms jitter of an LO signal at 100GHz must be reduced to less than 50fs to satisfy –30dB EVM for 64-QAM. To achieve such low rms jitter, the bandwidth of a PLL must be extended to suppress the poor phase noise (PN) of a sub-THz VCO, but it cannot sufficiently filter the high in-band PN that is amplified by a large multiplication factor (M). Thus, to date, cascaded PLLs with

👥 作者与机构

Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi

Korea Advanced Institute of Science and Technology, Daejeon, Korea