A 48-to-82.5GHz CMOS Split-Tail Gilbert-Cell Frequency Doubler Achieving 11% PAE at 8.5dBm Output Power

📋 论文概要

该论文提出了一种基于改进型Gilbert单元的48-82.5GHz频率倍频器，通过分裂尾跨导并在开关四象限晶体管上并联电容实现AC短路，使DC偏移降低开关占空比，从而提升功率转换增益和效率。该设计在28nm FDSOI CMOS工艺下实现了8.5dBm输出功率和11%的峰值PAE，解决了毫米波VCO相位噪声和调谐范围不足的问题。

💡 主要创新点

• 采用分裂尾跨导结构，将Gilbert单元中尾电流源分成两部分，分别驱动两个差分对，提高设计灵活性。
• 在开关四象限晶体管的栅极和源极之间并联电容，形成AC短路路径，利用稳态DC偏移减小开关占空比，从而增强功率转换增益和效率。
• 实现48-82.5GHz的宽工作频率范围，在毫米波频段取得11%的高PAE和8.5dBm输出功率。

🏷 关键词

📄 原文摘要

Abstract A 48-to-82.5GHz frequency doubler in 28nm FDSOI CMOS using a modified Gilbert cell is presented. The tail transconductors are split and the switching-quad transistors AC-shorted by capacitors. DC offset builds up across the capacitors, reducing the switching-quad duty cycle in steady state. This mechanism enhances power-conversion gain and efficiency. Measurements show 8.5dBm output power at 11% PAE. Despite sustained research, mm-wave CMOS VCOs still struggle to meet the phase-noise and tuning-range requirements of emerging wireless communication systems and radar sensors. As a result, frequency multiplication from a lower-frequency VCO remains the only viable solution for high-performance mm-wave frequency synthesis. In this context, CMOS frequency doublers continue to attract research attention, with several recent works reporting notable performance improvements. the resulting differential IR drop to generate the DC offset, thereby driving iO toward zero

👥 作者与机构

Jismal Jamal1, Lorenzo Piotto2, Federico Vecchi3, Mahmoud M. Pirbazari3, Andrea Mazzanti1

University of Pavia, Pavia, Italy, 2Fondazione Chips-IT, Pavia, Italy, 3STMicroelectronics, Pavia, Italy