Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 Ring-oscillator (RO)-based digital PLLs (DPLLs) are well-suited for multi-PLL-integrated SoC designs owing to their compactness and immunity to magnetic coupling. However, their inferior phase noise (PN) limits their utilization in low-jitter applications. To tackle this, both the quantization noise (Q-noise) and RO PN (PNRO) need to be well suppressed. Previous techniques reported in the literature to address these limitations are often prone to process, voltage, and temperature (PVT) variations or are energy inefficient. Figure 19.1.1 reviews popular PN-quantization and PNRO-suppression schemes. The classic time-todigital-converter (TDC) scheme suffers from high Q-noise due to the technology-limited delay (τ) and simultaneously high τ variation over PVT, thus significantly compromising the PN performance and loop stability. Alternatively, the optimal-threshold-TDC (OT-TDC)
Yu Duan1, Yan Zhu1, Rui P. Martins1,2, Chi-Hang Chan1
University of Macau, Macau, China