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ISSCC 2022Session 23 · FREQUENCY SYNTHESIZERSClocking & PLLs

A 68.6fsrms-Total-Integrated-Jitter and 1.56µs-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching

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📋 论文概要

本文提出了一种基于II型齿轮变速技术的分数N bang-bang锁相环,实现了68.6fsrms的总集成抖动和1.56µs的锁定时间,解决了移动通信中对超低抖动和频率捷变本地振荡器的需求。

💡 主要创新点

核心指标
68.6fsrms jitter, 1.56µs locking time
重要性
发表年份
ISSCC 2022

🏷 关键词

低抖动快速锁定分数N bang-bang PLLII型齿轮变速

📄 原文摘要

Luca Avallone2, Alessio Santiccioli1, Agata Iesurum3, Giovanni Steffan2, Dmytro Cherniak2, Luca Bertulessi1, Andrea Bevilacqua3, Carlo Samori1, Andrea Leonardo Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy Infineon Technologies, Villach, Austria 3 University of Padova, Padova, Italy 1 2 *Equally Credited Authors (ECAs) To pursue the ever-growing trend in mobile data-rates, modern transceivers exploit carrier aggregation and high-order modulations, at the price of calling for ultra-low jitter (below 100fs) and frequency-agile local oscillators. Although the bang-bang digital-PLL (BBPLL) architecture can meet the stringent 5G jitter requirements at low power consumption and silicon area [1], its inability to quickly recover from a frequency jump, caused by the narrow linear range of a bang-bang phase detector (BBPD), has so far prevented its application when frequency agility is an important requirement. A highresolution and wide-range time-to-digital converter (TDC)

👥 作者与机构

Simone Mattia Dartizio*1, Francesco Buccoleri*1, Francesco Tesolin1,

分类:Clocking & PLLs · 年份:ISSCC 2022