A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

📋 论文概要

本文提出一种级联PLL架构，由第一级LC-PLL和第二级RO-PLL组成，并采用可编程双对齐技术，实现了204fs的积分抖动（100kHz至100MHz）。该设计有效抑制了带内相位噪声，解决了传统PLL在大分频比下抖动恶化的问题。

💡 主要创新点

• 提出LC-PLL与RO-PLL级联架构，结合两阶段优势实现低抖动。
• 引入可编程双对齐技术，进一步优化相位噪声并提高系统灵活性。

🏷 关键词

📄 原文摘要

communications, require deep-subpicosecond integrated phase jitter [1]. Their in-band phase noise (PN) can be adversely affected by flicker noise and a large feedback frequency-division ratio, N. Cascaded PLLs are a recent trend in addressing this problem [2-4]. They are composed of two stages: the 1st stage (PLL #1) receives an external frequency reference FREF to generate a filtered reference of several GHz feeding into the 2nd stage (PLL #2) that features a lower division ratio and a wide bandwidth for better overall jitter performance. Although the cascaded PLL can chose from various combinations of oscillators, e.g., LC-tank and ring-oscillator (RO), the PLL #2 using an RO can benefit from a small size, easy integration, wide

👥 作者与机构

Tsung-Hsien Tsai1, Ruey-Bin Sheen1, Sheng-Yun Hsu1, Ya-Tin Chang1,

Chih-Hsien Chang1, Robert Bogdan Staszewski2 TSMC, Hsinchu, Taiwan University College Dublin, Dublin, Ireland 1 2 Many PLLs, including those used for mm-wave 5G