技术领域

Clocking & PLLs

127 篇相关论文 (2008–2026)

ISSCC 2020 Session 17 Clocking & PLLs
A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth
Pratap Tumkur Renukaswamy1,2, Nereo Markulic1, Sehoon Park1,2,
continuous-wave (FMCW) radars are a viable solution for high-resolution indoor localization and tracking applications. The fast saw-tooth FMCW chirp needs to be synthesized with a short ramp time, large chirp bandwidth (
Anirudh Kankuppe1,2, Qixian Shi 1, Piet Wambacq1,2, Jan Craninckx1 ime
ISSCC 2020 Session 17 Clocking & PLLs
A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM
Yizhe Hu1, Xi Chen1, Teerachot Siriburanon1, Jianglin Du1, Zhong Gao1,
Ireland 1 2 Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular for 5G millimeter-wave (mmW) frequency generation [1,2] due to their ability to achieve ultra-low jitter (<100fs). How
Vivek Govindaraj1, Anding Zhu1, Robert Bogdan Staszewski1,2 University
ISSCC 2020 Session 17 Clocking & PLLs
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
Mario Mercandelli1, Alessio Santiccioli1, Angelo Parisi1, Luca Bertulessi1,
oscillators for 5G wireless transceivers require rms integrated jitter below 100fs to enable spectrally efficient modulation schemes, such as high-order quadrature amplitude modulation (QAM), at millimeter-wave carrier f
Dmytro Cherniak2, Andrea Leonardo Lacaita1, Carlo Samori1, Salvatore L
ISSCC 2020 Session 17 Clocking & PLLs
A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting
Yiyang Shu, Huizhen Jenny Qian, Xun Luo
The development of millimeter-wave (mmW) multiple-band systems for the 5G wireless and point-to-point backhaul communication requires ultra-wideband signal sources with low phase noise. However, with increasing parasitic
University of Electronic Science and Technology of China, Chengdu, Chi
ISSCC 2020 Session 17 Clocking & PLLs
A 66fsrms Jitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking
Alessio Santiccioli1, Mario Mercandelli1, Luca Bertulessi1, Angelo Parisi1,
substantial increase in mobile data-rates, enabled by the 5G standard, calls for significantly lower integrated jitter of the local oscillator with respect to previous generations, with requirements below 90fs rms for mi
Dmytro Cherniak2, Andrea Leonardo Lacaita1, Carlo Samori1, Salvatore L
ISSCC 2019 Session 16 Clocking & PLLs
GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur
Michael Peter Kennedy1,2, Yann Donnelly1,3, James Breslin4,
Stefano Tulisi4, Sanganagouda Patil4, Ciarán Curtin4, Stephen Brookes4, Brian Shelly4, Patrick Griffin4, Michael Keaveney4 University College Dublin, Dublin, Ireland Microelectronic Circuits Centre Ireland, Dublin, Irelan
ISSCC 2019 Session 16 Clocking & PLLs
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur
Zunsong Yang1, Yong Chen1, Shiheng Yang1, Pui-In Mak1,
Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at l
ISSCC 2019 Session 16 Clocking & PLLs
A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS
Luigi Grimaldi, Luca Bertulessi, Saleh Karman, Dmytro Cherniak,
Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino Politecnico di Milano, Milan, Italy Digital phase-locked loops (DPLLs) have been demonstrated to achieve excellent performance as fractional-N fr
ISSCC 2019 Session 16 Clocking & PLLs
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and -70dBc Fractional Spurs
Dihang Yang1, Asad Abidi1, Hooman Darabi2, Hao Xu1, David Murphy2,
standards, such as WiFi 802.11ax with a 1024-QAM mode, require RF clocks with extremely low integrated phase error and low spurs. Because of their good scalability, digital phase-locked loops (DPLLs) have been widely stu
Hao Wu2, Zhaowen Wang3 University of California, Los Angeles, CA Broad
ISSCC 2019 Session 16 Clocking & PLLs
A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax
Fei Song1, Yu Zhao1, Bart Wu1, Litian Tang1, Leon Lin1, Behzad Razavi2
11ax WLAN standard improves the throughput by supporting 1024-QAM in a channel bandwidth of 160MHz, demanding extremely low jitter values for the transmitter (Tx) and the receiver (Rx) synthesizers. Recent work has achie
Ubilinx Technology, San Jose, CA 2 University of California, Los Angel
ISSCC 2019 Session 16 Clocking & PLLs
A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation
Szu-Yao Hung, Sudhakar Pamarti
There is need for a low-power, compact, means of generating multiple, low-jitter, spectrally pure, clock signals at different frequencies using a single reference oscillator, both in wireline and wireless applications, o
University of California, Los Angeles, CA
ISSCC 2019 Session 16 Clocking & PLLs
A -246dB Jitter-FoM 2.4GHz Calibration-Free RingOscillator PLL Achieving 9% Jitter Variation Over PVT
Xiaofeng Yang1, Chi-Hang Chan1, Yan Zhu1, Rui P. Martins1,2
Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Low-jitter phase-locked loops (PLLs) are critical building blocks in various systems, including wireless and wireline communications and ADCs. LC osci
University of Macau, Macau, China
ISSCC 2019 Session 16 Clocking & PLLs
A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization
Juyeop Kim*, Heein Yoon*, Younghyun Lim*, Yongsun Lee,
have ultra-low phase noise (PN) is very important for the design of RF transceivers (TRXs) for high-data-rate 5G systems. Direct-RF-sampling TRXs also require high-frequency clock signals, having extremely low integrated
Yoonseo Cho, Taeho Seong, Jaehyouk Choi Ulsan National Institute of Sc
ISSCC 2019 Session 16 Clocking & PLLs
A 265µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS
Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon,
exponentially increased for Systems on Chip (SoC). A fractional-N phase-locked loop (PLL) is one of the most important building blocks in SoCs for a variety of applications, such as frequency synthesis for wireless trans
Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi O
ISSCC 2018 Session 7 Clocking & PLLs
A 445F2 Leakage-Based Physically Unclonable Function with Lossless Stabilization Through Remapping for IoT Security
Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee
With the advent of the IoT era, billions of devices are connected to networks, and assuring sufficient security at low cost is a critical concern. Physically Unclonable Functions (PUFs) have drawn increasing attention as
Sungkyunkwan University, Suwon, Korea
ISSCC 2018 Session 7 Clocking & PLLs
A PUF Scheme Using Competing Oxide Rupture with Bit Error Rate Approaching Zero
Meng-Yi Wu, Tsao-Hsin Yang, Lun-Chun Chen, Chi-Chang Lin,
Hao-Chun Hu, Fang-Ying Su, Chih-Min Wang, James Po-Hao Huang, Hsin-Ming Chen, Chris Chun-Hung Lu, Evans Ching-Sung Yang, Rick Shih-Jye Shen eMemory, Hsinchu, Taiwan Security is critical to today’s interconnected world, a
ISSCC 2018 Session 7 Clocking & PLLs
A Secure Camouflaged Logic Family Using PostManufacturing Programming with a 3.6GHz Adder Prototype in 65nm CMOS at 1V Nominal VDD Fig. 7.6.3 shows the Shmoo plots for the pre-programmed adder design under no stress (baseline), 60 seconds reverse function stress from baseline, and 60 seconds boost stress from baseline. The 60 second reverse function stress fully alters the logic function of the pre-programmed gates. The stress voltage is 3V, resulting in a current density and voltage drop per leg of 18.4mA/μm2 and 2.67V.
Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai
With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production
Carnegie Mellon University, Pittsburgh, PA
ISSCC 2018 Session 7 Clocking & PLLs
An Enhanced-Security Buck DC-DC Converter with True-Random-Number-Based Pseudo Hysteresis Controller for Internet-of-Everything (IoE) Devices
Wen-Hau Yang1, Li-Cheng Chu1, Shang-Hsien Yang1, Yan-Jiun Lai1,
Internet-of-Everything (IoE) devices are concerned, strong security and low electromagnetic interference (EMI) are design requirements for power management to guarantee personal data protection. [1] is robust under power
Shao-Qi Chen1, Ke-Horng Chen1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen
ISSCC 2018 Session 7 Clocking & PLLs
A 0.3-to-1.2V Frequency-Scalable Fractional-N ADPLL with a Speculative Dual-Referenced Interpolating TDC
Minseob Lee1, Shinwoong Kim2, Hwasuk Cho1, Jahyun Koo1,
Power management with dynamic frequency control has been a key feature in battery-operated systems. It effectively reduces energy consumption by the microcontroller in mobile systems towards meeting ultra-low-power const
Kwang-Hee Choi2, Jin-Hyeok Choi2, Byungsub Kim1, Hong-June Park1, Jae-
ISSCC 2018 Session 7 Clocking & PLLs
A 0.02mm2 Fully Synthesizable Period-Jitter Sensor Using Stochastic TDC Without Reference Clock and Calibration in 10nm CMOS Technology
Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun Kim, Taeik Kim, Hyungjong Ko
becomes challenging. To effectively manage the tight jitter performance required by an SoC, the clock quality should be directly evaluated at every point where the clock is used in the SoC. In previous work [1-3], on-chi
Samsung Electronics, Hwaseong, Korea With the increasing clock speed a
ISSCC 2018 Session 7 Clocking & PLLs
A 0.0056mm2 All-Digital MDLL Using Edge
Re-Extraction, Dual-Ring VCOs and a 0.3mW, Block-Sharing Frequency Tracking Loop Achieving
292fsrms Jitter and -249dB FOM Shiheng Yang1, Jun Yin1, Pui-In Mak1, Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Multiplying delay-locked loop
ISSCC 2017 Session 19 Clocking & PLLs
A 0.2V Trifilar-Coil DCO with DC-DC Converter in
16nm FinFET CMOS with 188dB FOM, 1.3kHz
Resolution, and Frequency Pushing of 38MHz/V for Energy Harvesting Applications QTrifialr=Im(ZTotal)/Re(ZTotal). The total QTrifilar is a combination of Q-factors of the three coils. Two thick metals and one ultra-thick
ISSCC 2017 Session 19 Clocking & PLLs
A 2.4GHz RF Fractional-N Synthesizer with 0.25fREF BW
Long Kong, Behzad Razavi
The loop bandwidth of conventional RF fractional-N synthesizers has been limited to about fREF/10 despite the use of methods that suppress the ΔΣ-modulator quantization noise [1-4]. The trade-off between the loop bandwid
University of California, Los Angeles, CA
ISSCC 2017 Session 19 Clocking & PLLs
A 0.0049mm2 2.3GHz Sub-Sampling Ring-Oscillator PLL with Time-Based Loop Filter Achieving -236.2dB Jitter-FOM
Jeffrey (Tsung-Hao) Chuang, Harish Krishnaswamy
High-performance phase-locked loops (PLLs) and clock multipliers with low jitter/phase noise are essential for numerous applications, such as digital microprocessors and SoCs, wireline/optical links, data converters and
Columbia University, New York, NY
ISSCC 2017 Session 19 Clocking & PLLs
A 50-to-66GHz 65nm CMOS All-Digital Fractional-N PLL with 220fsrms Jitter
Ahmed Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh
Digital-PLL frequency synthesizers for wireless applications have become popular in the sub-10GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the integer-N type [1]. This is due to li
Carnegie Mellon University, Pittsburgh, PA
ISSCC 2017 Session 19 Clocking & PLLs
A PVT-Robust -39dBc 1kHz-to-100MHz IntegratedPhase-Noise 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop Using the Averages of Phase Deviations for mm-Band 5G Transceivers
Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
have an ultra-wide bandwidth in a mm-wave band. A big challenge of a 5G transceiver is to generate ultra-low-PN (phase noise) local-oscillator (LO) signals to suppress integrated PN (IPN) over such an extremely wide band
Ulsan National Institute of Science and Technology, Ulsan, Korea To me
ISSCC 2017 Session 19 Clocking & PLLs
A Fundamental-Frequency 114GHz Circular-Polarized
Radiating Element with 14dBm EIRP, -99.3dBc/Hz, Phase-Noise at 1MHz Offset and 3.7% Peak Efficiency
viable choice for imaging/sensing applications by offering faster scan time and robust source-detector alignment compared to linear radiation [1]. Power-efficient generation of a low-noise, highpower mm-wave/THz circular
Peyman Nazari, Saman Jafarlou, Payam Heydari University of California,
ISSCC 2014 Session 21 Clocking & PLLs
A Pulling Mitigation Technique for Direct-Conversion Transmitters
Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi
Despite versatility and low power consumption, direct-conversion transmitters suffer from a fundamental drawback: the local oscillator disturbance by the power amplifier, through unwanted electromagnetic or capacitive co
Broadcom, Irvine, CA
ISSCC 2014 Session 21 Clocking & PLLs
A 1.8mW PLL-Free Channelized 2.4GHz ZigBee Receiver Utilizing Fixed-LO TemperatureCompensated FBAR Resonator
Keping Wang1, Jabeom Koo1, Richard Ruby2, Brian Otis1
Avago Technologies, San Jose, CA 1 feed forward the RF signal into M4 and M6 to reduce the differential signal imbalance. Simulated results show that the gain and phase imbalance of the proposed LNA are improved by 5.6dB
University of Washington, Seattle, WA,
ISSCC 2014 Session 21 Clocking & PLLs
A 2.4-to-5.3GHz Dual-Core CMOS VCO with Concentric 8-Shaped Coils
Luca Fanori1,2, Thomas Mattsson3, Pietro Andreani1,3
now at Marvell, Pavia, Italy, 3 Ericsson Modems, Lund, Sweden 1 2 Despite recent attempts to relax the phase-noise demands on voltage-controlled oscillators (VCOs) for cellular communications [1], mainstream radios requi
Lund University, Lund, Sweden,
ISSCC 2014 Session 21 Clocking & PLLs
A 3.24-to-8.45GHz Low-Phase-Noise ModeSwitching Oscillator
Mazhareddin Taghivand1,2, Kamal Aggarwal1, Ada S. Y. Poon1
Qualcomm, San Jose, CA 1 2 VCO design for cellular applications to achieve universal coverage for a wide range of frequencies (400MHz to 3700MHz) in different standards and meeting stringent out-of-band and in-band phase
Stanford University, Stanford, CA,
ISSCC 2014 Session 21 Clocking & PLLs
A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS
Viki Szortyka1,2, Qixian Shi1,2, Kuba Raczkowski1, Bertrand Parvais1,
11ad standard, the LO synthesis needs both a low-noise VCO and low in-band phase noise. In the PLL shown in this paper, a QVCO with superharmonic passive coupling exhibits a large swing and low phase noise even with a 0.
Maarten Kuijk2, Piet Wambacq1,2 imec, Heverlee, Belgium, 2Vrije Univer
ISSCC 2014 Session 21 Clocking & PLLs
A 2GHz 130mW Direct-Digital Frequency Synthesizer with a Nonlinear DAC in 55nm CMOS
Taegeun Yoo1, Yun-Hwan Jung1, Hong Chang Yeoh1,2, Yong Sin Kim1,
employed in many frequency-agile communication systems because of their wide bandwidth, fine frequency resolution, and fast frequency-hopping characteristics. Recent developments in DDFSs are towards enhancing performanc
Sung-Mo Kang3, Kwang-Hyun Baek1 Chung-Ang University, Seoul, Korea, 2A
ISSCC 2014 Session 21 Clocking & PLLs
A 2.3GHz Fractional-N Dividerless Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise
Po-Chun Huang, Wei-Sung Chang, Tai-Cheng Lee
Recently, dividerless PLL architectures, including sub-sampling PLLs [1] and injection-locked PLLs [2], have been reported to achieve superior phase noise with respect to conventional PLL architectures. However, these di
National Taiwan University, Taipei, Taiwan
ISSCC 2014 Session 21 Clocking & PLLs
A 1.7GHz MDLL-Based Fractional-N Frequency Synthesizer with 1.4ps RMS Integrated Jitter and 3mW Power Using a 1b TDC
Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin,
Salvatore Levantino, Carlo Samori, Andrea L. Lacaita Politecnico di Milano, Milan, Italy The introduction of inductorless frequency synthesizers into standardized wireless systems still requires a high level of innovatio
ISSCC 2013 Session 23 Clocking & PLLs
A Wideband Fractional-N Ring PLL with FractionalSpur Suppression Using Spectrally Shaped Segmentation
Tsung-Kai Kao1, Che-Fu Liang1, Hsien-Hsiang Chiu1, Michael Ashburn2
Fractional-N PLLs play an important role in both wireless and wireline circuits. Finer timing resolution is needed to reduce the quantization noise in the phase domain. In conventional designs, a phase interpolator (PI)
MediaTek, Hsinchu, Taiwan, 2MediaTek, Woburn, MA
ISSCC 2013 Session 23 Clocking & PLLs
A Divider-Less Sub-Harmonically Injection-Locked PLL with Self-Adjusted Injection Timing
I-Ting Lee1, Yen-Jen Chen2, Shen-Iuan Liu1, Chewn-Pu Jou2,
frequency synthesis, and data conversion. In [1,2], a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In [3-5], a low-phase-noise sub-harmonically injection-locked PL
Fu-Lung Hsueh2, Hsieh-Hung Hsieh2 National Taiwan University, Taipei,
ISSCC 2013 Session 23 Clocking & PLLs
A 3.1mW Phase-Tunable Quadrature-Generation Method for CEI 28G Short-Reach CDR in 28nm CMOS
Kanupriya Bhardwaj1, Sriram Narayan2, Sergey Shumarayev3, Thomas Lee1
phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature gener
Stanford University, Stanford, CA, Inphi, Santa Clara, CA, 3 Altera, S
ISSCC 2013 Session 23 Clocking & PLLs
An 8Gb/s 0.65mW/Gb/s Forwarded-Clock Receiver Using an ILO with Dual Feedback Loop and Quadrature Injection Scheme
Ji-Hwan Seol1, Young-Ju Kim1, Sang-Hye Chung1, Kyoung-Soo Ha2,
low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data j
Seung-Jun Bae2, Jung-Bae Lee2, Joo Sun Choi2, Lee-Sup Kim1 KAIST, Daej
ISSCC 2013 Session 23 Clocking & PLLs
An 8Gb/s 1.5mW/Gb/s 8-Tap 6b NRZ/PAM-4 Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22nm CMOS
Marcel Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Brändli,
feed-forward equalization (FFE)
Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Th
ISSCC 2013 Session 23 Clocking & PLLs
A 5.5Gb/s 5mm Contactless Interface Containing a 50Mb/s Bidirectional Sub-Channel Employing Common-Mode OOK Signaling
Ken’ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno
replace existing interfaces that use wire harnesses and connectors, are expected to be employed in many applications because they would provide such features as immunity to mechanical failures due to vibration/friction,
Renesas Electronics, Kawasaki, Japan High-volume, mm-range, contact-le
ISSCC 2013 Session 23 Clocking & PLLs
A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended Short-Haul Serial Link in 28nm CMOS for Advanced Packaging Applications
John W. Poulton1, William J. Dally2, Xi Chen2, John G. Eyles1,
Thomas H. Greer III1, Stephen G. Tell1, C. Thomas Gray1 The receiver (right of Fig. 23.3.2) consists of a common-gate amplifier [3,4], biased so that its output swing is symmetric around the switching threshold of a CMOS
ISSCC 2013 Session 23 Clocking & PLLs
A Scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-Lane Parallel I/O in 32nm CMOS
Mozhgan Mansuri1, James E. Jaussi1, Joseph T. Kennedy1,
Tzu-Chien Hsueh1, Sudip Shekhar1, Ganesh Balamurugan1, Frank O’Mahony1, Clark Roberts1, Randy Mooney2, Bryan Casper1 Intel, Hillsboro, OR, 2Intel, Mapleton, UT 1 High-performance computing (HPC) systems demand aggressive
ISSCC 2013 Session 23 Clocking & PLLs
A 0.1pJ/b 5-to-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45nm CMOS SOI
Yong Liu1, Ping-Hsuan Hsieh*, Seongwon Kim1, Jae-sun Seo1,
J. Watson, Yorktown Heights, NY, in transparent mode and the other is in data latching mode. The output stability is improved by newly-introduced weak pull-up transistor M7 that helps maintain the voltage level of node G
Robert Montoye1, Leland Chang1, Jose Tierno**, Daniel Friedman1 IBM T
ISSCC 2013 Session 20 Clocking & PLLs
A 50-to-930MHz Quadrature-Output Fractional-N Frequency Synthesizer with 770-to-1860MHz SingleInductor LC-VCO and Without Noise Folding Effect for Multistandard DTV Tuners
Zhangwen Tang1, Xiongxiong Wan1,2, Minggui Wang1,2, Jie Liu1
Ratio Microelectronics, Shanghai, China 1 2 There are many Digital TV (DTV) standards around the world, such as DVB-T/C/H in Europe, ATSC-C/M/H in North America, TDMB in China, ISDB-T in Japan and DMB-T in South Korea. I
Fudan University, Shanghai, China,
ISSCC 2013 Session 20 Clocking & PLLs
A 2.4psrms-jitter Digital PLL with Multi-Output BangBang Phase Detector and Phase-Interpolator-Based Fractional-N Divider
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
time-to-digital converter(TDC)-based architectures [1] to avoid significant complexity and power overhead due to such a critical building block [2-4]. Architectures based on bang-bang phase detectors are very attractive
Infineon Technologies, Villach, Austria In the field of digital PLLs,
ISSCC 2013 Session 20 Clocking & PLLs
A 57.9-to-68.3GHz 24.6mW Frequency Synthesizer with In-Phase Injection-Coupled QVCO in 65nm CMOS
Xiang Yi, Chirn Chye Boon, Hang Liu, Jia Fu Lin, Jian Cheng Ong, Wei Meng Lim
systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to genera
Nanyang Technological University, Singapore, Singapore Under the influe
ISSCC 2013 Session 20 Clocking & PLLs
A 56.4-to-63.4GHz Spurious-Free All-Digital Fractional-N PLL in 65nm CMOS
Wanghua Wu1, Xuefei Bai1,2, Robert Bogdan Staszewski1, John R. Long1
University of Science and Technology of China, Hefei, China 1 2 Frequency synthesis at mm-Waves is still dominated by analog PLLs, although all-digital PLLs (ADPLLs) [1] have been widely explored below 10GHz. The major o
Delft University of Technology, Delft, The Netherlands,
ISSCC 2013 Session 20 Clocking & PLLs
A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz Minimum Noise FOM Using Inductor Splitting for Tuning Extension
Enrico Mammei1, Enrico Monaco2, Andrea Mazzanti1, Francesco Svelto1
Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due
University of Pavia, Pavia, Italy, 2STMicroelectronics, Pavia, Italy
ISSCC 2013 Session 20 Clocking & PLLs
Third-Harmonic Injection Technique Applied to a 5.87-to-7.56GHz 65nm CMOS Class-F Oscillator with 192dBc/Hz FOM
Masoud Babaie1,2, Robert Bogdan Staszewski1
Aktieve Rangschikkings Monolitische Microgolf Onderdelen B.V., Delft, The Netherlands 1 resonance frequency fosc2 to ‘snap’ to it if both are within the locking range [5]. The locking range is wide enough (±5%) due to th
Delft University of Technology, Delft, The Netherlands,