Clocking & PLLs

Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator [1] has been proposed to improve the efficiency of the standard Class-B oscillator (most often ref

more popular as possible alternatives to conventional analog charge-pump-based PLLs [1]. Currently, most of the ADPLLs are based on a time-to-digital converter (TDC) utilizing inverter delay chains. There have been treme

Sampling clock jitter significantly degrades the circuit performance and dynamic range of an ADC [1]. This paper presents a 570fsrms integrated-jitter 1.21GHz PLL with a hybrid loop. A ring VCO has a much inferior phase

System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC h

In the design of a fractional-N PLL, the trade-off between in-band VCO noise and ΔΣ quantization noise constrains the choice of loop bandwidth. Various circuit schemes have been proposed to relax such constrains with noi

viable alternative to classical charge-pump analog PLLs [1-4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processe

In modern analog front-ends, there is an increasing demand on high- performance analog-to-digital converters (ADCs), which require high sampling frequency and low-jitter sampling clock. This makes low-jitter phase-locked

Carlo Samori, Andrea L. Lacaita Politecnico di Milano, Milan, Italy State-of-the-art digital fractional-N PLLs intended for modern wireless systems make use of high-resolution and high-linearity time-to-digital converter

Cedric Dufis1, Pierre Busson1, Pierre Vincent2, Didier Belot1, Pascal Urard1 1 STMicroelectronics, Crolles, France CEA-LETI-Minatec, Grenoble, France 3 STMicroelectronics, Grenoble, France 2 This work shows a complete PL

David Stegmeir, Li Jin RFMD, San Jose, CA Because of higher performance requirements, infrastructure transceivers have historically employed lower levels of on-chip integration than their handset counterparts. One of the

Fujitsu Laboratories, Yokohama, Japan Fujitsu Laboratories, Kawasaki, Japan 2 This paper describes a 0.3mm2 and a 90M-to-770MHz range low spurious fractional-N synthesizer, with which mobile receivers for Japanese terres

Oshima1, Bruce Andrew Doyle1, Roland Bakalski2, Richard Joseph DeSantis1, Anand Thiruvengadam1, Charles Lin Wang1, Gerry Robert Talbot1, Emerson S Fang1 1 AMD, Sunnyvale, CA Global Foundries, Dresden, Germany 2 As proces

Shouvik Mukherjee1, Cathy Lee1, Vadim Tsinker4, Sathi Perumal5, Benjamin Soto6, Niveditha Arumugam1, Bruno W Garlepp1 1 SiTime, Sunnyvale, CA University of California, Los Angeles, CA 3 Global Foundries, Sunnyvale, CA 4

Recently, on-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces such as DDR I/F and HDMI (for initial negotiation), and SoCs.

Physical Logic, Bnei Brak, Israel 1 that there is no current flow through the selected transistor Mn. This eliminates calibration nonlinearity due to the parasitic resistances of the switch transistors which are placed i

In nanoscale CMOS processes, the leakage current [1,2] is becoming one of the important issues to cope with for high-performance analog and mixed-signal integrated circuits. For digital circuits, the leakage current resu

Tsinghua University, Beijing, China Samsung Electronics, Hwasung, Korea 2 As data rate of wireline applications increases, clock skew becomes a significant portion of the overall timing margin and directly affects the BE

Ratio Microelectronics, Shanghai, China 1 2 There is a high demand for high-performance tuners to meet the digital video broadcasting-terrestrial (DVB-T) standard. Often the DVB-T tuners employ a double-conversion zero-I

In this situation, the output of OAI gate switching from ‘0’ to ‘1’ indicates the occurrence of current compensation. When an EXT missing edge occurs, the DC=’0’ implies the amount of E recording in full adder is decreme

University of Twente, Enschede, The Netherlands National Semiconductor, Santa Clara, CA 2 A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transce

Intel, Chandler, AZ 1 2 A major source of close-in phase noise in ∆Σ fractional-N frequency synthesizers is noise-folding due to the nonlinear behavior of the combined phasefrequency detector (PFD)/charge-pump (CP) circu

Sirenza Microdevices, San Jose, California The traditional analog approach for frequency control of a crystal oscillator (XO) uses a varactor embedded into the structure of the XO to tune its frequency. This method requi

Gordy Carichner1, Eric Marsman1, Nam Nguyen2, Sundus Kubba1, Si Nguyen2, Jon Kuhn1, Richard B. Brown3 1 Mobius Microsystems, Detroit, MI, 2Mobius Microsystems, Sunnyvale, CA University of Utah, Salt Lake City, UT 3 The q

Gerard J. M. Wienk, Bram Nauta University of Twente, Enschede, Netherlands Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Figure 19.5.1 shows

Offering less than 1ppm frequency resolution, a ΔΣ fractional-N PLL enables flexible frequency planning and reliable spread spectrum modulation for digital clock generation [1, 2]. Use of low-cost ring VCOs however, mand

area of intense investigation, motivated by low supply headroom and poor analog performance in ultra-scaled CMOS. RF frequency synthesis is particularly amenable to a digital architecture and has already seen integration

University of California at San Diego, La Jolla CA NextWave Broadband, San Diego, CA A major problem with fractional-N PLLs is that their phase noise contains fractional spurs, i.e., spurious tones at multiples of fref t