A Leakage-Suppression Technique for Phase-Locked Systems in 65nm CMOS

📋 论文概要

该论文针对65nm CMOS工艺中锁相环（PLL）的泄漏电流问题，提出了一种泄漏抑制技术。该技术有效降低了相位/频率检测器（PFD）、分频器和压控振荡器（VCO）中泄漏电流引起的相位噪声、抖动和共模电压漂移，提升了PLL系统的性能。

💡 主要创新点

• 提出一种适用于PLL中PFD和分频器的泄漏电流抑制电路，减少带内相位噪声和抖动。
• 针对VCO的泄漏电流问题，设计了一种共模电压稳定技术，防止泄漏电流改变VCO工作点。

🏷 关键词

📄 原文摘要

In nanoscale CMOS processes, the leakage current [1,2] is becoming one of the important issues to cope with for high-performance analog and mixed-signal integrated circuits. For digital circuits, the leakage current results in a high stand-by power consumption. For analog circuits, it degrades the accuracy and performance. PLLs are widely used in various wireline and wireless communication systems. For a phase/frequency detector (PFD) and a divider in a PLL, the leakage current increases the in-band phase noise and jitter. For a VCO, the leakage current alters the common-mode voltage, and as a result the VCO may not operate at a low frequency [3]. For a charge pump (CP) and a loop filter, the leakage current induces a steady phase error and jitter. It is because the leakage current charges or discharges the loop filter while the CP is off. Since a PLL usually needs a large capacitor in its loop filter, the MOS

👥 作者与机构

Chao-Ching Hung, Shen-Iuan Liu

National Taiwan University, Taipei, Taiwan