A 2.2GHz 7.6mW Sub-Sampling PLL with −126dBc/Hz In-Band Phase Noise and 0.15psrms Jitter in 0.18µm CMOS

📋 论文概要

本文提出一种2.2GHz的子采样锁相环（PLL），采用子采样鉴相器/电荷泵（PD/CP）直接对VCO输出进行采样，避免了传统PLL中的分频器，从而在低功耗下实现极低的带内相位噪声和抖动。解决了高频时钟生成中功耗与噪声折衷的问题。

💡 主要创新点

• 提出基于子采样的PD/CP结构，无需频率分频器即可锁定VCO，显著降低功耗和带内相位噪声。
• 在0.18μm CMOS工艺下实现2.2GHz输出，功耗仅7.6mW，带内相位噪声-126dBc/Hz，抖动0.15ps rms，性能优于常规PLL。

🏷 关键词

📄 原文摘要

University of Twente, Enschede, The Netherlands National Semiconductor, Santa Clara, CA 2 A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power. In a classical PLL, a VCO is locked to a reference clock Ref by a feedback loop with a divider, PD/CP, and loop filter. Both the VCO and the loop components contribute to PLL phase noise, the VCO noise dominating out-of-band and the loop noise in-band. In an optimized PLL, the two types of noise contribute equally to the output jitter [1, 2] and thus, are equally important. This work focuses on the loop noise and presents a technique to reduce it significantly.

👥 作者与机构

Xiang Gao1, Eric A. M. Klumperink1, Mounir Bohsali2, Bram Nauta1