A 0.4-to-1.6GHz Low-OSR ∆Σ DLL with SelfReferenced Multiphase Generation

📋 论文概要

该论文提出了一种工作频率为0.4至1.6GHz的低过采样率ΔΣ DLL，采用自参考多相生成技术，解决了传统模拟延迟线受PVT变化影响的问题，实现了宽频率范围内精确的时钟相位控制。

💡 主要创新点

• 提出自参考多相生成技术，无需外部参考时钟即可产生多相时钟。
• 采用低过采样率ΔΣ调制，降低功耗和面积。
• 实现宽频率范围0.4-1.6GHz的DLL操作。

🏷 关键词

📄 原文摘要

Tsinghua University, Beijing, China Samsung Electronics, Hwasung, Korea 2 As data rate of wireline applications increases, clock skew becomes a significant portion of the overall timing margin and directly affects the BER performance. A variable delay line (VCDL) or a DLL is widely used for elastic timing control not only in source-synchronous serial links but also in clock-and-datarecovery systems for further enhancing the BER performance. The conventional analog delay line, however, suffers from PVT variations, and calibrating the analog delay line brings substantial design efforts. For better testability and robust operation, a digitally controlled delay line is preferred. The semidigital DLL [1] or the all-digital DLL [2] provides more robust delay control, but achieving fine timing resolution such as sub-ps is still challenging due to an algorithmic jitter problem. The ∆Σ DLL shown in Fig. 23.5.1 performs oversampled phase interpolation

👥 作者与机构

Xueyi Yu1, Woogeun Rhee1, Zhihua Wang1, Jung-Bae Lee2, Changhyun Kim2