⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种边缘缺失补偿器，用于快速锁定和宽锁定范围的锁相环（PLL）。通过检测外部和内部缺失边缘并调整电荷泵电流，解决了传统PLL在宽锁定范围内锁定速度慢的问题。
In this situation, the output of OAI gate switching from ‘0’ to ‘1’ indicates the occurrence of current compensation. When an EXT missing edge occurs, the DC=’0’ implies the amount of E recording in full adder is decremented by 1. When an INT missing edge occurs, the DC=’1’ implies the amount is incremented by 1. The full adder is used to count E and the amount is decoded as the control signals to the ECP. 1 2 An ideal phase detector (PD) produces an output signal whose DC value is linearly proportional to the phase difference (∆θ) between the phases of its two periodic inputs. In practice, however, the transfer curve of the PD may not be linear or even monotonic for large ∆θ. With a nonlinear PD, the transient response of PLL cannot be easily formulated and slow down the acquisition
Ting-Hsu Chien1, Chi-Sheng Lin1, Ying-Zong Juang1,
Chun-Ming Huang1, Chin-Long Wey1,2 National Chip Implementation Center, Hsinchu, Taiwan National Central University, Jhongli, Taiwan INT and UC are zeros (an INT edge missing)