A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

📋 论文概要

该论文提出了一种基于环形DCO的5.2GHz分数N数字PLL，通过1/8 DTC范围缩减技术实现了188fsrms的低抖动和-243dB的FoMjitter，解决了环形振荡器高抖动的问题。

💡 主要创新点

• 提出1/8 DTC范围缩减技术，有效降低DTC的非线性影响，提升抖动性能
• 基于环形DCO实现低抖动分数N数字PLL，达到与LC-PLL相当的FoM
• 通过扩展环路带宽的设计策略，克服环形振荡器的高抖动问题

🏷 关键词

📄 原文摘要

*Equally Credited Authors (ECAs) Modern SoCs for advanced wireless/wired applications integrate an increasing number of PLLs. 5G TRXs require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Multilane high-speed serial links for high data throughput also require many PLLs. To maximize the area efficiency, ring-oscillator (RO)-based digital PLLs (DPLLs) are the obvious alternative to the conventional LC-oscillator analog PLLs (LC-PLLs). To overcome the well-known problem of the high jitter of an RO, the general design guideline is to extend the loop bandwidth. However, this strategy cannot be applied readily to a fractional-N architecture, since a wide bandwidth cannot prevent various in-band noise sources from degrading the overall jitter. Recently, many techniques have been presented to suppress those noise sources. The optimal-threshold TDC (OT TDC) [1] and the noise-shaping BBPD [2] are efficient techniques to reduce the

👥 作者与机构

Chanwoong Hwang*, Hangi Park*, Taeho Seong, Jaehyouk Choi

KAIST, Daejeon, Korea