A Differential Series-Resonance CMOS VCO with Pole-Convergence Technique Achieving 202.1dBc/Hz FoMTA at 10MHz Offset

📋 论文概要

该论文提出了一种差分串联谐振CMOS VCO，采用极点收敛技术，在10MHz偏移处实现了202.1 dBc/Hz的FoMTA。旨在解决低相位噪声VCO设计中传统多核方法带来的面积和功耗增加问题。

💡 主要创新点

• 提出了差分串联谐振结构，通过极点收敛技术改善相位噪声与FoM。
• 在10MHz偏移处实现202.1 dBc/Hz的FoMTA，优于传统设计。
• 无需增加核心数量即可获得高性能，降低了面积与功耗开销。

🏷 关键词

📄 原文摘要

sought for various applications, such as high-speed wireless/wireline communications, high-speed ADC/DACs, etc. According to Leeson’s formula (Fig. 19.5.1 top-left), achieving lower PN requires a larger VTANK or a smaller L. Since the maximum VTANK is constrained by technology and minimum L is limited by the ‘small-inductor’ issue [1], the multicore technique can be employed. By coupling N VCO cores, the equivalent parallel resistance RP is scaled down by N, and the PN is improved by 10log(N), while the FoM is kept unchanged ideally. However, as the number of cores increases, so do the silicon area and potential mismatch among cores, while the design complexity, such as the power-delivery network, also becomes more challenging. Using series-resonance VCOs (SR-VCOs) offers an alternative

👥 作者与机构

Jinhua Guo, Pei Qin, Haoshen Zhu, Xiang Yi, Wenjie Feng, Wenquan Che, Quan Xue

South China University of Technology, Guangzhou, China Voltage-controlled oscillators with ultra-low phase noise (PN) are extensively