A 13GHz Charge-Pump PLL Achieving 15.8fsrms Integrated Jitter and -98.5dBc Reference Spur

📋 论文概要

该论文提出了一种13GHz电荷泵锁相环，通过改进电荷泵和环路滤波器设计，实现了15.8fsrms的集成抖动和-98.5dBc的参考杂散，解决了亚采样锁相环中因二进制频移键控效应导致的大参考杂散问题。

💡 主要创新点

• 采用新型电荷泵结构，有效抑制了BFSK效应引起的参考杂散
• 优化了环路滤波器设计，在保持低抖动的同时进一步降低了杂散水平

🏷 关键词

📄 原文摘要

wideband data converters, have imposed extremely stringent demands on phase-locked loops (PLLs) for lower jitter and spurs. Benefiting from high phase-detector (PD) gain, sub-sampling PLLs (SSPLLs) achieve superior jitter performance with low in-band phase noise (PN) [1,2]. Nevertheless, they suffer from large reference spurs due to the binary-frequency-shiftkeying (BFSK) effects (Fig. 19.11.1 top left). Sampling PLLs (SPLLs) preserve the high detection gain without periodically modulating the voltage-controlled oscillator (VCO) [3-5]. However, the maximum PN suppression is typically limited by the available Kslope, which is in turn set by the parasitic capacitor CP as shown in Fig. 19.11.1 (top right). Chargepump PLLs (CPPLLs) are the most widely employed architectures due to their robust

👥 作者与机构

Depeng Sun1, Feng Bu1, Qixian Ye1, Shijie Li1, Yuan Gao1, Bowen Wang1, Hao Xu2,

Na Yan2, Shubin Liu1, Zhangming Zhu1 Xidian University, Xi’an, China Fudan University, Shanghai, China 1 2 Modern communication systems, such as RF-sampling systems utilizing