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÷ Nint AUX RO Non-overlapping Clock Generator + - + CBaux[2:0] + - + + - Vref Vb Vo V+ + Gm FFNC On: 157 fs Fractional-N Mode 60MHz × 52 ÷ 30 × 31 × 2 (c) Vctrlmain 60MHz × 52 ÷ (30+2-13) × (31+2-13) × 2 6.7GHz (d) fout 6.2~6.8GHz - α[k] MMD-based Q-Noise Cancellation FFNC On: 145 fs Integer-N Mode Feedforward RO Noise Cancellation UGB V- ÷ Nmain FFNC Off: 357 fs + - ÷ Naux α 6.4GHz FFNC Off: 358 fs L1: 382 pH L2: 421 pH Vctrlaux AUX Integer-N SPLL (fBW1 = 10MHz) faux 3.1~3.4GHz (b) Frac. Spur ×7 Main LCO Gm MASH 1-1-1 6.4GHz Vctrlaux + - + AUX/Main SPDs with identical design (a) OUT+ IN- CBaux[2:0] fref 60MHz OUT- IN+ Frac. Spur 6.7GHz QEC Off FFNC Off: 442 fs Vref fmain 100~160MHz Vin1 fdiv2 3.1~3.4GHz CBmain[4:0] Vout Vin2 Main Fractional-N SPLL (fBW2 = 1MHz) ÷2 Figure 27.2.3: Circuit implementation of the proposed PLL. (a) Fractional-N Mode 60MHz × 53 ÷ (20+2-11) × (21+2-11) × 2 fBW2 fBW1 Main PLL PN FFNC On Naux x 1 Naux x 1.5 Naux x 2 fref/2 (d) α=2-10 α=2-9 -84.7dBc (-72.7dBc) 203kHz 102kHz -84.8dBc (-72.8dBc) 60MHz × 53 ÷ 20 × (21+2-11) × 2 This Work H. Zhang ISSCC'25 D. Yang ISSCC'22 SPD/SPD D. Xu JSSC'25 Pulse Gen. +BBPD G. Jin JSSC'24 M. Mercandelli JSSC'22 W. Wu JSSC'21 SPD SPD SPD Phase Detector Noise Cancell./ Filter. Technique Calibration required? SPD/PFDCP SPD/XORPD MMD-QEC +FFNC MMD-QEC Harmonicmixing DTC-QEC DTC-QEC DTC-QEC DTC-QEC No No No Yes Yes Yes Yes VCO Type Ring+LC LC+LC LC+LC Ring+LC LC LC LC 60 82 74 50 100 500 76.8x2 6.2 to 6.8 4.7 to 5.7 25 to 28 6.5 to 8 3.3 to 4.5 11.9 to 14.1 5 to 7 157 (1k to 100M) 95.9 (1k to 100M) 88 (10k to 40M) 191 (10k to 10M) 203 (10k-100M) 58.2 (1k-100M) 80~95 (10k-100M) %72.7 %70.6 %70 %52.7 %57 %63.2 <%72 Reference Frequency [MHz] Output Frequency [GHz] (c) Fractional-N Mode Figure 27.2.4: Measured PN near 6.4GHz in (a) integer-N mode and (b) fractional-N mode with QEC on, FFNC on or off; measured PN near 6.7GHz in (c) fractional-N mode with QEC on, FFNC on or off and (d) fractional-N mode with FFNC on, QEC on or off. (b) RO, AUX PLL PN Normalized to Main PLL Freq. Main PLL PN FFNC Off FFNC On: 160 fs ×31 Non-overlapping Clock Generator Integrated Jitter [fs] In-band Fractional Spur [dBc] Power [mW] 17.2 21.2 12.9 14.2 2.4 18 14.2 FoM* [dB] %243.7 %247.1 %250 %242.9 %250.0 %252.1 %250.4 ~ %249.0 FoMREF** [dB] %235.9 %238.0 %241.3 %235.9 %240.0 %235.1 %241.5 ~ %240.1 CMOS Process [nm] Active 2 Area [mm ] 65 65 7 65 40 28 14 0.16 0.25 0.24 0.48 0.36 0.16 0.31 Figure 27.2.5: (a) FFNC robustness verification based on measurement results; (b) *FoM = 10log((Power/1mW)*(Jitter/1s)2) **FoMref = 10log((Power/1mW)*(Jitter/1s)2)+10log(fref/10MHz) measured fractional spur levels at near-integer channels; (c)(d) measured output Figure 27.2.6: Performance comparison of the proposed PLL with prior-art designs. spectra with fractional spurs. Power (mW) AUX 0.9 5% Loop RO 5.8 34% Main 1.7 10% Loop DSM 0.4 2% LCO 8.4 49% Total 17.2 100% 850μm 480μm LCO Main LF FFAMP AUX SPD/Div. AUX GM /LF AUX/Main MMDs DSM Main SPD/GM RO Area (mm2) AUX 0.010 6% Loop RO 0.006 4% Main 0.023 14% Loop DSM 0.003 2% LCO 0.119 74% Total 0.162 100% Figure 27.2.7: Die micrograph (left); measured power consumption and area (right). • 2026 IEEE International Solid-State Circuits Conference 979-8-3315-8936-3/26/$31.00 ©2026 IEEE

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