A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL

📋 论文概要

本文提出了一款0.65V供电、工作频率10.4-11.8GHz的分数N采样锁相环（PLL），实现了73.8fs rms的极低抖动、-271.5dB的FoM以及-61dBc的带内分数杂散。解决了低电压下高频PLL的噪声与杂散挑战。

💡 主要创新点

• 采用0.65V超低供电电压实现10.4-11.8GHz高频分数N采样PLL，显著降低功耗。
• 通过采样PLL架构并结合数字校准技术，在低电压下达到73.8fs rms的极低抖动和-61dBc的带内分数杂散。

🏷 关键词

📄 原文摘要

stage DPD is implemented digitally. Thanks to its cascaded structure, our HC-DPD with a 6b calibration coefficient can be split into two-stage 3b DPDs, enabling significant hardwareoverhead reduction compared to the conventional DPD with the same number of bits in the calibration coefficient. Xinyu Shen1,2, Zhao Zhang1,2, Yixi Li1,2, Junjie Chen1,2, Xiangjian Kong1, Nan Qi1,2, Jian Liu1,2, Nanjian Wu1,2, Liyuan Liu1,2 The convergence simulation results demonstrate the correct functionality of our HC-DPD and the unsuitability of the conventional DPD for cascaded implementations [Fig. 19.8.2(bottom-left)]. As shown in Fig. 19.8.2(bottom-right), with a large DTC INL (INLCDTC) of 4.6ps (simulated) and an ideal SPD and R-FDAC, the ADH-DPD is used to calibrate each CWDTC of the 3b DTC. Under these conditions, no obvious noise folding is exhibited in the simulated PN because the ADH-DPD compensates the DTC INL physically without a ∆ΣM.

👥 作者与机构

Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61dBc, In-band Fractional Spur in 40nm CMOS