A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM

📋 论文概要

该论文提出了一种亚100MHz参考驱动的25-28GHz分数N锁相环，解决了高频下参考相位噪声被大分频比N放大以及振荡器电容调谐导致Q值下降的难题，实现了-250dB的FoM。

💡 主要创新点

• 采用亚100MHz参考驱动架构，降低参考路径噪声放大倍数，改善相噪和杂散性能。
• 通过优化环路带宽和振荡器设计，在25-28GHz频段内达到-250dB FoM的优异能效比。

🏷 关键词

📄 原文摘要

>25GHz inevitably faces the problems of a large closed-loop gain fvco/fref = N. Phase noise and spurs on the reference input and from other sources in the loop referred to its input are amplified by N. A narrow loop bandwidth must be used to limit the resulting jitter. However, now the loop is unable to adequately suppress the oscillator phase noise, leading to a difficult trade-off. At these operating frequencies, the oscillator is inherently noisier since a capacitor bank for digital tuning greatly compromises the overall LC tank quality factor (Q). Therefore, for low output jitter, the synthesizer either needs to allocate disproportionately more current to the VCO than at sub-10GHz, use a sub-10GHz VCO with a frequency multiplier [1], or

👥 作者与机构

Dihang Yang1, David Murphy1, Hooman Darabi1, Arya Behzad1, Asad Abidi2,

Stephen Au1, Sraavan Mundlapudi1, Kejian Shi1, Weiyu Leng2 Broadcom, San Jose, CA University of California, Los Angeles, CA 1 2 A mm-wave frequency synthesizer with output