A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique

📋 论文概要

该论文提出了一种基于多路径反馈技术的分数-N锁相环，实现了34fsrms的抖动性能和-255.5dB的FoM，解决了高参考频率在实际应用中不实用的问题。

💡 主要创新点

• 提出多路径反馈技术，有效降低相位噪声和抖动。
• 在较低参考频率下实现亚100fs的抖动性能，适合低成本大规模部署。

🏷 关键词

📄 原文摘要

modulation schemes, such as 4K-QAM, and impose stringent phase-noise requirements on frequency synthesizers. In the past few years, an increasing number of frac-N PLLs with excellent jitter performance, i.e., sub-100fs, have been reported [1-6]. Some prior works utilize relatively high reference frequencies and benefit from lower noise multiplication ratios, which can help improve jitter performance. However, high reference frequencies of 150 to 500MHz are not practical for cost-effective mass deployment. This work is based on an analog PLL with several developed techniques to achieve competitive jitter and FoM. The reference frequency is 80MHz, and the PLL operates from 7.3 to 9.5GHz. In a conventional fractional-N PLL, the time spread of the feedback clock due to delta-sigma modulation (DSM) leads to the DSM noise at the PLL output. Besides, the well-known

👥 作者与机构

Chao-Ching Hung, Chih-Hsien Shen, Chien-Li Lin, Mou Tzou, Kevin Fong, Yu-Li Hsueh

MediaTek, Hsinchu, Taiwan State-of-the-art advanced-communication standards adopt sophisticated