A 20GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2fs Jitter and -76.5dBc Worst-Case Fractional Spur

📋 论文概要

本文提出了一种20GHz频率合成器，采用杂散整形调制器（SSM）技术有效抑制了由切片间失配引起的非线性，实现了46.2fs的集成抖动和-76.5dBc的最差分数杂散。该设计在28nm CMOS工艺中实现，取得了-251.4dB的FoM和-102.6dB的FoMIBS，解决了高速收发器对低抖动、低杂散分数N频率合成器的需求。

💡 主要创新点

• 提出杂散整形调制器（SSM）技术，通过抑制切片间失配引起的非线性来降低分数杂散。
• 实现了20GHz频率合成器同时具有超低抖动（46.2fs）和超低最差分数杂散（-76.5dBc），并达到极佳的FoM和FoMIBS指标。

🏷 关键词

📄 原文摘要

Abstract In this paper, a frequency synthesizer is proposed with low fractional spur and low jitter, featuring a spur-shaping-modulator (SSM) technique that suppresses the nonlinearity arising from inter-slice mismatch. Implemented in 28nm CMOS, the prototype synthesizer is measured to achieve a 46.2fs integrated jitter, a −84.1dBc near-integer fractional spur, and a -76.5dBc worst-case fractional spur with a −251.4dB FoM and −102.6dB FoMIBS. A low-jitter low-spur fractional-N frequency synthesizer is crucial in high-speed transceivers. Since the jitter contribution of the quantization noise from the delta-sigma modulator (DSM) has become significant in low-jitter frequency synthesizers, numerous quantization-noise reduction techniques have recently been investigated to mitigate this issue [1–11]. Using a digital-to-time converter (DTC) is a popular solution as it could generate a fine-resolution

👥 作者与机构

Zonglin Ye, Yuxuan Sun, Longxiang Hou, Yuhan Ding, Yixuan Wen, Hongyang Zhang, Xinlin Geng, Qian Xie, Shiheng Yang, Zheng Wang

University of Electronic Science and Technology of China, Chengdu, China