A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications

📋 论文概要

提出了一种基于SRAM的全数字存内计算多瓦片神经网络加速器，采用18nm FD-SOI工艺，支持最高4位精度，能效达40-310 TOPS/W。解决了传统SRAM存内计算模拟/混合信号设计中的精度和功耗问题，通过全数字架构实现高吞吐和高能效。

💡 主要创新点

• 全数字SRAM存内计算架构，无需ADC/DAC，避免模拟不匹配和精度损失。
• 多瓦片（multi-tiled）设计，支持灵活扩展和高效数据流，适用于深度神经网络。
• 结合FD-SOI工艺的体偏置技术，在宽电压下实现40-310 TOPS/W的超宽能效范围。

🏷 关键词

📄 原文摘要

Harsh Rawat2, Hitesh Chawla2, Abhijith VS2, Paolo Zambotti4, Akhilesh Sharma2, Carmine Cappetta1, Michele Rossi1, Antonio De Vita1, Francesca Girardi1 STMicroelectronics, Cornaredo, Italy STMicroelectronics, Noida, India 3 STMicroelectronics, Geneva, Switzerland 4 STMicroelectronics, Agrate, Italy *Equally Credited Authors (ECA) 1 2 In-memory computing (IMC) has been proposed to address compute-intensive datadriven AI workloads, using either SRAM or emerging memory technologies such as PCM, RRAM, and MRAM offering different trade-offs when used as an integrated computing device at the system level. A notable distinction is between digital vs. analog IMC. The latter uses either resistive or capacitive sharing techniques to maximize row parallelism, but at the expense of inaccuracies and accumulation resolution loss due to device variations across PVT and the limited SNR and dynamic range of the ADC/readout

👥 作者与机构

Giuseppe Desoli*1, Nitin Chawla*2, Thomas Boesch*3, Manuj Ayodhyawasi*2,