⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种在22nm FinFET工艺中实现的D波段接收器，集成了PLL和ADC，实现了128Gb/s的数据率和1.95pJ/b的能效，解决了先前工作中关键模块缺失的问题。
Somnath Kundu1, Peter Sagazio1, Hariprasad Chandrakumar1, Thomas Brown1, Brent Carlton1, Christopher Hull4, Steven Callender1, Stefano Pellerano1 Intel, Hillsboro, OR, 2Intel, Santa Clara, CA, 3now with Apple, Sunnyvale, CA now with Amazon, Redmond, WA 1 4 Recent work has shown the ability of mm-wave (30 to 100GHz) and sub-THz (100 to 300GHz) receivers to support large bandwidths needed to meet growing data-rate demands in a variety of applications, from dielectric waveguide [1] to wireless [2,3] links. Unfortunately, prior art either excludes the integration of critical receiver blocks (e.g. PLL, ADC) or contains complete but power-hungry LO generation [2]. A critical challenge in demonstrating sub-THz receivers with an integrated ADC is the limited availability of process nodes that provide efficient performance for both RF and mixed-signal/digital circuits simultaneously. This work presents a D-band (140GHz) receiver (RX) which
Abhishek Agrawal1, Amy Whitcombe2, Woorim Shin3, Ritesh Bhat1,