A 4nm 6163-TOPS/W/b 4790-TOPS/mm2/b SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update disabled, to save power, in 8b mode. The INWIDTH[1:0] bus controls the XIN width: 00 for 8b, 01 for 12b, and 10 for 16b modes. To support a signed format with width flexibility, the first 4 cycles are signed 4b operations and the rest of the cycles are unsigned 4b operations, regardless of INWIDTH.

📋 论文概要

本文提出了一款基于4nm工艺的SRAM数字存内计算宏，支持位宽灵活性，实现了6163 TOPS/W/b的能效和4790 TOPS/mm²/b的面积效率。通过混合阈值电压设计和加法器树流水线优化，平衡了性能与漏电。

💡 主要创新点

• 采用混合Vt设计，在本地加法器和全局加法器中合理分配不同阈值电压器件，优化性能与漏电的平衡。
• 提出加法器树流水线结构，基于位宽灵活性进行动态重构，提升计算效率和密度。

🏷 关键词

📄 原文摘要

Chao-Kai Chuang1, Takeshi Hashizume2, Hao-Chun Tung1, Yao-Yi Liu1, Shin-Rung Wu1, Kerem Akarvardar3, Tan-Li Chou1, Hidehiro Fujiwara1, Yih Wang1, Yu-Der Chih1, Yen-Huei Chen1, Hung-Jen Liao1, Tsung-Yung Jonathan Chang1 Figure 7.4.3 describes the overall layout floorplan, the transistor threshold voltage (Vt) selection, and the adder tree pipeline. In the DCIM, the MAC array uses a mixed-Vt design to balance performance and leakage; We checked device count and gate delay in the local adders and global adders to place mixed-Vt devices in adder tree. Due to the tree structure of adder, the SRAM bit cell array and adders in the early stage of the adder tree occupies >75% of total device in adder tree. Therefore, we use high-Vt devices for the SRAM array and local adders to reduce leakage. On the other hand, low-Vt devices are used in other portions of adder: semi-global and global adders, shifter, and accumulator.

👥 作者与机构

Haruki Mori1, Wei-Chang Zhao1, Cheng-En Lee1, Chia-Fu Lee1, Yu-Hao Hsu1,