A 70.85–86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation

📋 论文概要

该论文提出了一种PVT不敏感的8b字并行模拟计算存内（ACIM）设计，通过将全局VREF路由从8b 256节点大幅减少至16节点，实现了16倍面积缩减，同时避免了多转换和数字位移带来的时钟复杂度、增益、偏移、线性度和系统能量问题，最终在70.85–86.27 TOPS/W的能效范围内实现高性能计算。

💡 主要创新点

• 通过16倍减少全局VREF路由节点，显著降低面积开销，并简化时钟和数字逻辑。
• 提出后处理放松（Post-Processing Relaxation）技术，改善PVT不敏感性和系统能效。
• 采用2次8bIN 4bW MAC操作完成8bIN 8bW的计算，平衡精度与硬件成本。

🏷 关键词

📄 原文摘要

the 16× reduction of the global VREF routing (from 8b 256 nodes to 16 nodes), the area is 16× smaller. Without the multi-conversions of MSB/LSB parts and digital bit shifting, the clock complexity, gain, offset, linearity, and system energy are also dramatically improved. Sung-En Hsieh1, Chun-Hao Wei1, Cheng-Xin Xue1, Hung-Wei Lin1, Wei-Hsuan Tu1, En-Jui Chang1, Kai-Taing Yang1, Po-Heng Chen1, Wei-Nan Liao1, Li Lian Low2, Chia-Da Lee1, Allen-CL Lu1, Jenwei Liang1, Chih-Chung Cheng1, 8bIN 8bW is finished by 2 8bIN 4bW MAC for this work, Figure. 7.6.3 shows a proposed Tzung-Hung Kang1 MediaTek, Hsinchu, Taiwan 2 MediaTek, Singapore, Singapore 1 Tiny-machine learning (TinyML) and artificial intelligence-of-things (AIoT) present new opportunities for machine-intelligent applications with stringent energy constraints. To conserve system energy, high-power devices stay dormant and are woken up only when

👥 作者与机构

end of the compute phase, the converted voltage (V8bink = Dink[7:0] × VREF /(16 × 17)) is, buffered into the SRAM array with an >10b of linearity for the worst FF 125°C corner. By