A 1V 136.6dB-DR 4kHz-BW ∆Σ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18µm CMOS

📋 论文概要

本文提出了一种在0.18µm CMOS工艺下实现的1V电源电压、136.6dB动态范围、4kHz带宽的ΔΣ电流数字转换器。通过采用截断噪声成形的基线伺服环路技术，解决了低摆动电流信号在大慢变基线上的高动态范围读出难题，满足了光电容积描记、电化学传感等应用的需求。

💡 主要创新点

• 提出截断噪声成形的基线伺服环路(TNS-BSL)，有效抑制基线电流带来的大摆幅并降低截断噪声，从而显著提升动态范围。
• 采用ΔΣ调制架构结合电流输入前端，在1V低电压下实现136.6dB的高动态范围和4kHz的带宽，同时保持低功耗。
• 通过数字辅助校准和噪声整形技术，在0.18µm CMOS工艺中实现了低噪声和高线性度，适用于生物医学信号检测。

🏷 关键词

📄 原文摘要

Seungyeob Baik, Jaeha Kung, Ji-Woong Choi, Arup K. George, Junghyup Lee Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea Precise current measurements underpin emerging applications such as photoplethysmography (PPG), electrochemical sensing, and fast-scan cyclic voltammetry (FSCV) [1-6], where the signal is a low-swing current that rides on a large, slow-varying baseline. Therefore, readout systems need a dynamic-range (DR) >120dB, bandwidth (BW) >1kHz, noise floor <1pArms/$Hz, and power <1mW (Fig. 32.3.1 left). To widen DR, prior front-ends employ a prediction DAC [1], threshold-filter-based feedback-loop [2], and a Reset-Then-Open (RTO) DAC [3]. However, they widen the DR by sacrificing BW or power (Fig. 32.3.1 right). For instance, [1] employing a prediction DAC requires a power-hungry digital backend, while [2] with a threshold-filter-based feedback-loop is BW-limited (~20Hz). In contrast, [3] achieves wide-DR and BW, but consumes >1mW

👥 作者与机构

Taeryoung Seol, Sehwan Lee, Geunha Kim, Samhwan Kim, Euiseong Kim,