A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer

📋 论文概要

本文提出一种单通道12位2GS/s的流水线ADC，采用临界阻尼环形放大器和时间域量化器，实现了对PVT变化的鲁棒性，无需校准即可获得高精度残差放大。

💡 主要创新点

• 采用临界阻尼环形放大器实现闭环残差放大，无需校准即可在PVT变化下保持增益稳定。
• 结合时间域量化器，在高速流水线ADC中实现高精度量化。

🏷 关键词

📄 原文摘要

Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 High-speed pipelined ADCs rely on fast and accurate residue amplification which often necessitates calibration, thus suffering from potential convergence issues, extra area/power overhead, and higher test costs. The state-of-the-art open-loop (OL) residue amplifiers (RAs) accommodate short amplification time [1] with decent calibration-free gain variation over PVT [2], reaching higher performance is challenging due to the absence of closed loop (CL) assistance. A ring-amp in a CL topology is a promising alternative, showing a 2× amplification within 420ps in a 16nm process [3]. Its ring-able nature, however, imposes a precise dead-zone (DZ) control for optimum performance over PVT in high-speed applications, which in turn loses the calibration-free characteristic common in CL architectures. This work presents a calibration-free critically damped ring

👥 作者与机构

Yuefeng Cao1, Minglei Zhang1, Yan Zhu1, Chi-Hang Chan1, R. P. Martins1,2

University of Macau, Macau, China