A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference

📋 论文概要

本文提出了一种28nm工艺下2-8比特可扩展的数字SRAM存内计算宏单元，通过无乘法神经网络设计方法和动态逻辑近似电路实现向量-向量运算，解决了数字CIM中近似计算精度损失和能效瓶颈问题。

💡 主要创新点

• 提出无乘法（multiply-less）的神经网络协同设计方法，消除乘法器开销，提升能效。
• 采用动态逻辑基近似电路，在保持精度的前提下降低数字CIM的功耗和面积。
• 实现2-8比特可扩展的数字SRAM CIM宏，支持灵活精度配置，适应不同神经网络需求。

🏷 关键词

📄 原文摘要

2 This paper presents a 2-to-8-b scalable digital SRAM-based CIM macro that is codesigned with a multiply-less neural-network (NN) design methodology and incorporates dynamic-logic-based approximate circuits for vector-vector operations. Digital CIMs enable high throughput and reliable matrix-vector multiplications (MVMs); however, digital CIMs face three major challenges to obtain further aggressive gains over conventional digital architectures: (1) prior digital CIMs exploiting approximate computation suffer from accuracy degradation [1]; (2) digital [2] and, as [3] predicted, mixed-signal CIMs [4], suffer from quadratic energy scaling with improving operand precision; (3) the tight and regular memory layout prevents CIMs from leveraging

👥 作者与机构

Yifan He1, Haikang Diao2, Chen Tang1, Wenbin Jia1, Xiyuan Tang2, Yuan Wang2,

Jinshan Yue3, Xueqing Li1, Huazhong Yang1, Hongyang Jia1, Yongpan Liu1 Tsinghua University, Beijing, China Peking University, Beijing, China 3 Chinese Academy of Sciences, Beijing, China