A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur

📋 论文概要

该论文提出了一种分数-N数字MDLL，通过注入误差加扰和后台三阶DTC延迟均衡器，实现了-67dBc的参考杂散抑制，解决了传统MDLL中DTC非线性导致的杂散问题。

💡 主要创新点

• 提出注入误差加扰技术，将DTC非线性误差随机化，降低分数杂散。
• 引入后台三阶DTC延迟均衡器，自适应校准DTC的非线性，提高线性度。
• 实现全数字MDLL架构，无需模拟校准，适合先进工艺缩放。

🏷 关键词

📄 原文摘要

University of Waterloo, Waterloo, Canada 1 2 Ring-oscillator (RO)-based injection-locked phase-locked loops (IL-PLLs) and multiplying delay-locked loops (MDLLs) are promising candidates for low-cost, highperformance clock generation, thanks to the largely suppressed phase noise of the RO due to the reference injection, small area, and technology-friendly scaling. For such architectures, the fractional-N operation is typically realized with a digital-to-time converter (DTC) to delay the reference-injection signal with a proper fractional-N phase shift such that it aligns with the RO phase at the injection node. However, the nonidealities of the DTC, including offset, gain, and integral-nonlinearity (INL) errors, introduce a periodic injection error into the RO and are key error mechanisms for generating reference and fractional spurious tones. Previous research on MDLLs or IL-PLLs that addressed DTC non-idealities falls mainly in two categories: DTC error

👥 作者与机构

Qiaochu Zhang1, Hsiang-Chun Cheng1, Shiyu Su1,2, Mike Shuo-Wei Chen1

University of Southern California, Los Angeles, CA