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ISSCC 2023Session 25 · RF TRANSCEIVER BUILDING BLOCKSRF & Wireless

A 1-to-5GHz All-Passive Frequency-Translational 4th-Order N-path Filter with Low-Power Clock Boosting for High Linearity and Relaxed Pdc-Frequency Trade-Off to the LO overlap while using 2× higher-duty-cycle clocks, thereby enabling a 4 to 5× higher operating frequency compared to higher-order N-path filters [1-5]. These inductors do not limit tuning range at all, unlike the coupling inductors in prior higherorder N-path topologies.

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📋 论文概要

本文提出了一种1至5GHz全无源频率转换四阶N路径滤波器,通过低功耗时钟提升技术实现高线性度。该滤波器利用基带椭圆低通负载的三个可编程电容(CF、CG、CB)来灵活调节带宽、选择性和带外抑制,解决了宽带可重构滤波器的线性度和功耗问题。

💡 主要创新点

重要性
发表年份
ISSCC 2023

🏷 关键词

N路径滤波器全无源频率转换时钟提升高线性度

📄 原文摘要

The higher-order N-path filter was designed to operate from 1 to 5GHz. The three capacitors CF, CG, and CB of the baseband elliptical-LPF loads are designed with a 5b control to program the bandwidth, selectivity, and OOB rejection. In particular, the clock frequency of the RF switches (left and right switches) decides the center frequency of the BPF, the capacitors CF and CG control the filter bandwidth and OOB rejection; the clock frequency of the elliptical LPF filters decides the offset frequency of the OOB notches from the BPF center; and the capacitor CB controls the bandwidth (or quality factor) of the OOB notches. The input to the RF-clock path is a differential LO at 2fclk,RF that is fed to a 3-stage, constant-phase polyphase filter to generate the 0°, 90°, 180°, and 270° phases at 2fclk,RF. The polyphase outputs drive two Current-Mode-Logic (CML)latch-based differential dividers, which are then fed to NAND gates and inverters to realize

👥 作者与机构

Aravind Nagulu1, Mingyu Yi 1, Yi Zhuang1, Sasank Garikapati2, Harish Krishnaswamy2

分类:RF & Wireless · 年份:ISSCC 2023