A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration

📋 论文概要

该论文提出了一种基于辅助PLL背景校准的分数输出分频器（FOD），工作频率范围为10-300MHz，实现了最差情况-80dBc的分数杂散性能。解决了传统多PLL方案面积大、功耗高、复杂度高的问题，以及DTC非线性导致的杂散问题。

💡 主要创新点

• 提出基于辅助PLL的背景校准技术，实时校正DTC非线性，显著降低分数杂散。
• 实现10-300MHz宽频率范围的分数输出分频，最差情况杂散仅-80dBc。
• 采用数字控制器与多模分频器（MMD）和DTC结合，实现低功耗、小面积的多时钟生成方案。

🏷 关键词

📄 原文摘要

generators to satisfy diverse specifications for different modules, such as microprocessors, memories, I/O interfaces, and power management. Conventionally, multiple PLLs are used in SoCs to provide various frequency outputs; however, this method incurs a considerable silicon area, power, cost, and the overall system complexity. Fractional output dividers (FODs), which are composed of a multi-modulus divider (MMD), a digitalto-time converter (DTC), and a digital controller, have been proved to be an effective method for multiple independent clock generation. However, the DTC characteristic is PVT sensitive, and any gain mismatch/integral nonlinearity (INL) generates large spurs, which degrade spectral purity and clock jitter. The traditional DTC-gain-calibration

👥 作者与机构

Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong,

Zhihua Wang, Baoyong Chi Tsinghua University, Beijing, China Modern system-on-chips (SoCs) integrate several independent on-chip clock