A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor

📋 论文概要

该论文提出了一种基于环形放大器的流水线时间交织逐次逼近寄存器型模数转换器，通过分裂型MDAC和开关参考去耦电容技术，在1GS/s采样率下实现了10-ENOB精度和10mW功耗，解决了高速高精度ADC功耗过高的问题。

💡 主要创新点

• 提出分裂型MDAC结构，将传统MDAC拆分为两个子DAC，降低了环形放大器的负载和功耗。
• 采用开关参考去耦电容技术，在保持阶段动态调整参考电压，提高了SAR ADC的线性度。
• 结合流水线与时间交织架构，利用低功耗SAR子ADC实现高速转换，避免了复杂的背景时序偏移校准。

🏷 关键词

📄 原文摘要

Next-generation wireless standards (e.g., WiFi-7) advancing towards wider bandwidth and higher order modulation require ADCs with GHz sampling rates and over 12b resolution. Although conventional pipelined ADCs can satisfy the speed and resolution specifications, their power is usually too high for handset applications, for which ≤10mW per channel is desired. Alternatively, time-interleaved (TI) ADCs achieve low power by harnessing efficient low-speed SAR sub-ADCs. However, background timing-skew calibrations bring considerable overhead and place limitations on the input signal. The pipeline/TI-SAR hybrid architecture places the interleaved SAR at the 2nd pipeline stage to avoid the timing skew problem [1]. As the SAR consumes low power and can run asynchronously, this greatly reduces the pipeline backend power and simplifies the clock distribution. However, the residue amplifier is still a power efficiency bottleneck as in a

👥 作者与机构

Mingtao Zhan, Lu Jie, Nan Sun

Tsinghua University, Beijing, China